요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
.. SPDX-License-Identifier: GPL-2.0
==================
Intel IPU6 Driver
==================
Author: Bingbu Cao <bingbu.cao@intel.com>
Overview
=========
Intel IPU6 is the sixth generation of Intel Image Processing Unit used in some
Intel Chipsets such as Tiger Lake, Jasper Lake, Alder Lake, Raptor Lake and
Meteor Lake. IPU6 consists of two major systems: Input System (ISYS) and
Processing System (PSYS). IPU6 are visible on the PCI bus as a single device, it
can be found by ``lspci``:
``0000:00:05.0 Multimedia controller: Intel Corporation Device xxxx (rev xx)``
IPU6 has a 16 MB BAR in PCI configuration Space for MMIO registers which is
visible for driver.
Buttress
=========
The IPU6 is connecting to the system fabric with Buttress which is enabling host
driver to control the IPU6, it also allows IPU6 access the system memory to
store and load frame pixel streams and any other metadata.
Buttress mainly manages several system functionalities: power management,
interrupt handling, firmware authentication and global timer sync.
ISYS and PSYS Power flow
------------------------
IPU6 driver initialize the ISYS and PSYS power up or down request by setting the
Buttress frequency control register for ISYS and PSYS
(``IPU6_BUTTRESS_REG_IS_FREQ_CTL`` and ``IPU6_BUTTRESS_REG_PS_FREQ_CTL``) in
function:
.. c:function:: int ipu6_buttress_power(...)
Buttress forwards the request to Punit, after Punit execute the power up flow,
Buttress indicates driver that ISYS or PSYS is powered up by updating the power
status registers.
.. Note:: ISYS power up needs take place prior to PSYS power up, ISYS power down
needs take place after PSYS power down due to hardware limitation.
Interrupt
---------
IPU6 interrupt can be generated as MSI or INTA, interrupt will be triggered when
ISYS, PSYS, Buttress event or error happen, driver can get the interrupt cause
by reading the interrupt status register ``BUTTRESS_REG_ISR_STATUS``, driver
clears the irq status and then calls specific ISYS or PSYS irq handler.
.. c:function:: irqreturn_t ipu6_buttress_isr(int irq, ...)
Security and firmware authentication
-------------------------------------
To address the IPU6 firmware security concerns, the IPU6 firmware needs to
undergo an authentication process before it is allowed to executed on the IPU6
internal processors. The IPU6 driver will work with Converged Security Engine
(CSE) to complete authentication process. The CSE is responsible of
authenticating the IPU6 firmware. The authenticated firmware binary is copied
into an isolated memory region. Firmware authentication process is implemented
by CSE following an IPC handshake with the IPU6 driver. There are some Buttress
registers used by the CSE and the IPU6 driver to communicate with each other via
IPC.
.. c:function:: int ipu6_buttress_authenticate(...)
Global timer sync
-----------------
The IPU6 driver initiates a Hammock Harbor synchronization flow each time it
starts camera operation. The IPU6 will synchronizes an internal counter in the
Buttress with a copy of the SoC time, this counter maintains the up-to-date time
until camera operation is stopped. The IPU6 driver can use this time counter to
calibrate the timestamp based on the timestamp in response event from firmware.
.. c:function:: int ipu6_buttress_start_tsc_sync(...)
DMA and MMU
============
The IPU6 has its own scalar processor where the firmware run at and an internal
32-bit virtual address space. The IPU6 has MMU address translation hardware to
allow that scalar processors to access the internal memory and external system
memory through IPU6 virtual address. The address translation is based on two
levels of page lookup tables stored in system memory which are maintained by the
IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
register and allows MMU to perform page table lookups.
The IPU6 driver exports its own DMA operations. The IPU6 driver will update the
page table entries for each DMA operation and invalidate the MMU TLB after each
unmap and free.
Firmware file format
====================
The IPU6 firmware is in Code Partition Directory (CPD) file format. The CPD
firmware contains a CPD header, several CPD entries and components. The CPD
component includes 3 entries - manifest, metadata and module data. Manifest and
metadata are defined by CSE and used by CSE for authentication. Module data is
specific to IPU6 which holds the binary data of firmware called package
directory. The IPU6 driver (``ipu6-cpd.c`` in particular) parses and validates
the CPD firmware file and gets the package directory binary data of the IPU6
firmware, copies it to specific DMA buffer and sets its base address to Buttress
``FW_SOURCE_BASE`` register. Finally the CSE will do authentication for this
firmware binary.
Syscom interface
================
The IPU6 driver communicates with firmware via the Syscom ABI. Syscom is an
inter-processor communication mechanism between the IPU scalar processors and
the CPU. There are a number of resources shared between firmware and software.
A system memory region where the message queues reside, firmware can access the
memory region via the IPU MMU. The Syscom queues are FIFO fixed depth queues
with a configurable number of tokens (messages). There are also common IPU6 MMIO
registers where the queue read and write indices reside. Software and firmware
function as producer and consumer of tokens in the queues and update the write
and read indices separately when sending or receiving each message.
The IPU6 driver must prepare and configure the number of input and output
queues, configure the count of tokens per queue and the size of per token before
initiating and starting the communication with firmware. Firmware and software
must use same configurations. The IPU6 Buttress has a number of firmware boot
parameter registers which can be used to store the address of configuration and
initialise the Syscom state, then driver can request firmware to start and run via
setting the scalar processor control status register.
Input System
============
IPU6 input system consists of MIPI D-PHY and several CSI-2 receivers. It can
capture image pixel data from camera sensors or other MIPI CSI-2 output devices.
D-PHYs and CSI-2 ports lane mapping
-----------------------------------
The IPU6 integrates different D-PHY IPs on different SoCs, on Tiger Lake and
Alder Lake, IPU6 integrates MCD10 D-PHY, IPU6SE on Jasper Lake integrates JSL
D-PHY and IPU6EP on Meteor Lake integrates a Synopsys DWC D-PHY. There is an
adaptional layer between D-PHY and CSI-2 receiver controller which includes port
configuration, PHY wrapper or private test interfaces for D-PHY. There are 3
D-PHY drivers ``ipu6-isys-mcd-phy.c``, ``ipu6-isys-jsl-phy.c`` and
``ipu6-isys-dwc-phy.c`` program the above 3 D-PHYs in IPU6.
Different IPU6 versions have different D-PHY lanes mappings, On Tiger Lake,
there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports,
see the PPI mmapping in ``ipu6-isys-mcd-phy.c`` for more information. On Jasper
Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports
maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock
lanes so IPU6 support maximum 6 CSI-2 ports.
.. Note:: Each pair of CSI-2 two ports is a single unit that can share the data
lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support
maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2
port 0 with 2 data lanes can work together with CSI-2 port 1 with 2
data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1
will not be available as the 4 data lanes are shared by CSI-2 port 0
and 1. The same applies to CSI ports 2/3, 4/5 and 7/8.
ISYS firmware ABIs
------------------
The IPU6 firmware implements a series of ABIs for software access. In general,
software firstly prepares the stream configuration ``struct
ipu6_fw_isys_stream_cfg_data_abi`` and sends the configuration to firmware via
sending ``STREAM_OPEN`` command. Stream configuration includes input pins and
output pins, input pin ``struct ipu6_fw_isys_input_pin_info_abi`` defines the
resolution and data type of input source, output pin ``struct
ipu6_fw_isys_output_pin_info_abi`` defines the output resolution, stride and
frame format, etc.
Once the driver gets the interrupt from firmware that indicates stream open
successfully, the driver will send the ``STREAM_START`` and ``STREAM_CAPTURE``
command to request firmware to start capturing image frames. ``STREAM_CAPTURE``
command queues the buffers to firmware with ``struct
ipu6_fw_isys_frame_buff_set``, software then waits for the interrupt and
response from firmware, ``PIN_DATA_READY`` means a buffer is ready on a specific
output pin and then software can return the buffer to user.
.. Note:: See :ref:`Examples<ipu6_isys_capture_examples>` about how to do
capture by IPU6 ISYS driver.
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
Intel IPU6 개요
1-22Bingbu Cao가 작성한 이 `GPL-2.0` 문서는 Intel Image Processing Unit의 6세대인 IPU6 driver를 설명합니다. IPU6는 Tiger Lake, Jasper Lake, Alder Lake, Raptor Lake, Meteor Lake 등의 Intel chipset에 사용되며, 크게 Input System(ISYS)과 Processing System(PSYS)으로 구성됩니다.
IPU6는 PCI bus에서 단일 multimedia controller로 보입니다. `lspci`에서는 `0000:00:05.0 Multimedia controller: Intel Corporation Device xxxx (rev xx)`와 같은 형태로 확인할 수 있습니다. PCI configuration space에는 driver가 MMIO register 접근에 사용하는 16 MB BAR가 있습니다.
.. SPDX-License-Identifier: GPL-2.0
==================
Intel IPU6 Driver
==================
Author: Bingbu Cao <bingbu.cao@intel.com>
Overview
=========
Intel IPU6 is the sixth generation of Intel Image Processing Unit used in some
Intel Chipsets such as Tiger Lake, Jasper Lake, Alder Lake, Raptor Lake and
Meteor Lake. IPU6 consists of two major systems: Input System (ISYS) and
Processing System (PSYS). IPU6 are visible on the PCI bus as a single device, it
can be found by ``lspci``:
``0000:00:05.0 Multimedia controller: Intel Corporation Device xxxx (rev xx)``
IPU6 has a 16 MB BAR in PCI configuration Space for MMIO registers which is
visible for driver.
Buttress 연결 계층
23-32IPU6는 Buttress를 통해 system fabric에 연결됩니다. Buttress는 host driver가 IPU6를 제어할 수 있게 하며, IPU6가 frame pixel stream과 기타 metadata를 저장하거나 불러오기 위해 system memory에 접근하도록 합니다.
Buttress가 관리하는 주요 system 기능은 power management, interrupt handling, firmware authentication, global timer synchronization입니다. 따라서 ISYS와 PSYS의 개별 기능보다 한 단계 위에서 IPU6 전체의 host 연동을 조정합니다.
Buttress
=========
The IPU6 is connecting to the system fabric with Buttress which is enabling host
driver to control the IPU6, it also allows IPU6 access the system memory to
store and load frame pixel streams and any other metadata.
Buttress mainly manages several system functionalities: power management,
interrupt handling, firmware authentication and global timer sync.
ISYS와 PSYS 전원 흐름
33-49IPU6 driver는 `ipu6_buttress_power(...)`에서 Buttress frequency control register인 `IPU6_BUTTRESS_REG_IS_FREQ_CTL`과 `IPU6_BUTTRESS_REG_PS_FREQ_CTL`을 설정해 ISYS와 PSYS의 power-up 또는 power-down 요청을 시작합니다.
Buttress는 이 요청을 Punit으로 전달합니다. Punit이 power-up 흐름을 실행하면 Buttress가 power status register를 갱신해 ISYS 또는 PSYS의 전원이 켜졌음을 driver에 알립니다.
Hardware 제약 때문에 순서가 중요합니다. Power-up에서는 ISYS가 PSYS보다 먼저 켜져야 하며, power-down에서는 PSYS가 먼저 꺼지고 ISYS가 나중에 꺼져야 합니다.
ISYS and PSYS Power flow
------------------------
IPU6 driver initialize the ISYS and PSYS power up or down request by setting the
Buttress frequency control register for ISYS and PSYS
(``IPU6_BUTTRESS_REG_IS_FREQ_CTL`` and ``IPU6_BUTTRESS_REG_PS_FREQ_CTL``) in
function:
.. c:function:: int ipu6_buttress_power(...)
Buttress forwards the request to Punit, after Punit execute the power up flow,
Buttress indicates driver that ISYS or PSYS is powered up by updating the power
status registers.
.. Note:: ISYS power up needs take place prior to PSYS power up, ISYS power down
needs take place after PSYS power down due to hardware limitation.
Interrupt 처리
50-59IPU6 interrupt는 MSI 또는 INTA로 생성될 수 있습니다. ISYS, PSYS, Buttress에서 event나 error가 발생하면 interrupt가 trigger됩니다.
Driver는 `BUTTRESS_REG_ISR_STATUS` interrupt status register를 읽어 원인을 확인하고 IRQ status를 clear한 다음, 해당 ISYS 또는 PSYS IRQ handler를 호출합니다. 이 진입점은 `ipu6_buttress_isr(int irq, ...)`입니다.
Interrupt
---------
IPU6 interrupt can be generated as MSI or INTA, interrupt will be triggered when
ISYS, PSYS, Buttress event or error happen, driver can get the interrupt cause
by reading the interrupt status register ``BUTTRESS_REG_ISR_STATUS``, driver
clears the irq status and then calls specific ISYS or PSYS irq handler.
.. c:function:: irqreturn_t ipu6_buttress_isr(int irq, ...)
보안과 firmware 인증
60-74IPU6 firmware는 내부 processor에서 실행되기 전에 인증을 거쳐야 합니다. IPU6 driver는 Converged Security Engine(CSE)과 협력하며, 실제 firmware 인증 책임은 CSE에 있습니다.
인증된 firmware binary는 격리된 memory 영역으로 복사됩니다. 인증 과정은 IPU6 driver와 CSE 사이의 IPC handshake로 구현되고, 양측은 여러 Buttress register를 통해 IPC 정보를 교환합니다. Driver 측 진입점은 `ipu6_buttress_authenticate(...)`입니다.
Security and firmware authentication
-------------------------------------
To address the IPU6 firmware security concerns, the IPU6 firmware needs to
undergo an authentication process before it is allowed to executed on the IPU6
internal processors. The IPU6 driver will work with Converged Security Engine
(CSE) to complete authentication process. The CSE is responsible of
authenticating the IPU6 firmware. The authenticated firmware binary is copied
into an isolated memory region. Firmware authentication process is implemented
by CSE following an IPC handshake with the IPU6 driver. There are some Buttress
registers used by the CSE and the IPU6 driver to communicate with each other via
IPC.
.. c:function:: int ipu6_buttress_authenticate(...)
Global timer 동기화
75-85IPU6 driver는 camera operation을 시작할 때마다 Hammock Harbor synchronization flow를 시작합니다. IPU6는 Buttress 내부 counter를 SoC time의 복사본과 동기화하며, 이 counter는 camera operation이 중지될 때까지 최신 시간을 유지합니다.
Driver는 firmware response event에 포함된 timestamp를 이 time counter와 대조해 보정할 수 있습니다. 동기화를 시작하는 함수는 `ipu6_buttress_start_tsc_sync(...)`입니다.
Global timer sync
-----------------
The IPU6 driver initiates a Hammock Harbor synchronization flow each time it
starts camera operation. The IPU6 will synchronizes an internal counter in the
Buttress with a copy of the SoC time, this counter maintains the up-to-date time
until camera operation is stopped. The IPU6 driver can use this time counter to
calibrate the timestamp based on the timestamp in response event from firmware.
.. c:function:: int ipu6_buttress_start_tsc_sync(...)
DMA와 MMU
86-100IPU6에는 firmware를 실행하는 자체 scalar processor와 내부 32-bit virtual address space가 있습니다. MMU address translation hardware는 scalar processor가 IPU6 virtual address를 통해 internal memory와 external system memory에 접근하도록 합니다.
Address translation은 system memory에 저장되고 IPU6 driver가 관리하는 2단계 page lookup table을 사용합니다. Driver는 level-1 page table base address를 MMU register에 설정하고, MMU가 page-table lookup을 수행하게 합니다.
IPU6 driver는 자체 DMA operation을 export합니다. 각 DMA operation마다 page-table entry를 갱신하고, unmap 및 free 뒤에는 MMU TLB를 invalidate합니다.
DMA and MMU
============
The IPU6 has its own scalar processor where the firmware run at and an internal
32-bit virtual address space. The IPU6 has MMU address translation hardware to
allow that scalar processors to access the internal memory and external system
memory through IPU6 virtual address. The address translation is based on two
levels of page lookup tables stored in system memory which are maintained by the
IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
register and allows MMU to perform page table lookups.
The IPU6 driver exports its own DMA operations. The IPU6 driver will update the
page table entries for each DMA operation and invalidate the MMU TLB after each
unmap and free.
CPD firmware file 형식
101-115IPU6 firmware는 Code Partition Directory(CPD) file format을 사용합니다. CPD firmware는 CPD header, 여러 CPD entry와 component로 구성됩니다. CPD component에는 manifest, metadata, module data의 세 entry가 있습니다.
Manifest와 metadata는 CSE가 정의하며 인증에 사용합니다. Module data는 IPU6 전용 firmware binary인 package directory를 담습니다. 특히 `ipu6-cpd.c`가 CPD firmware file을 parse·validate하고 package directory binary를 가져옵니다.
Driver는 package directory를 지정된 DMA buffer로 복사하고 그 base address를 Buttress `FW_SOURCE_BASE` register에 설정합니다. 마지막으로 CSE가 이 firmware binary를 인증합니다.
Firmware file format
====================
The IPU6 firmware is in Code Partition Directory (CPD) file format. The CPD
firmware contains a CPD header, several CPD entries and components. The CPD
component includes 3 entries - manifest, metadata and module data. Manifest and
metadata are defined by CSE and used by CSE for authentication. Module data is
specific to IPU6 which holds the binary data of firmware called package
directory. The IPU6 driver (``ipu6-cpd.c`` in particular) parses and validates
the CPD firmware file and gets the package directory binary data of the IPU6
firmware, copies it to specific DMA buffer and sets its base address to Buttress
``FW_SOURCE_BASE`` register. Finally the CSE will do authentication for this
firmware binary.
Syscom interface
116-136IPU6 driver는 Syscom ABI를 통해 firmware와 통신합니다. Syscom은 IPU scalar processor와 CPU 사이의 inter-processor communication mechanism입니다. Firmware와 software가 공유하는 resource에는 message queue가 놓이는 system memory 영역과 queue read/write index를 보관하는 공통 IPU6 MMIO register가 있습니다.
Firmware는 IPU MMU를 통해 queue memory에 접근합니다. Syscom queue는 token(message) 수를 설정할 수 있는 고정 깊이 FIFO입니다. Software와 firmware는 queue의 producer와 consumer로 동작하며, message를 보내거나 받을 때 write index와 read index를 각각 갱신합니다.
통신을 시작하기 전에 driver는 input/output queue 수, queue별 token 수, token 하나의 크기를 준비하고 설정해야 합니다. Firmware와 software는 반드시 같은 설정을 사용해야 합니다. Driver는 Buttress firmware boot parameter register에 configuration 주소를 기록하고 Syscom state를 초기화한 뒤, scalar processor control status register를 설정해 firmware의 시작과 실행을 요청합니다.
Syscom interface
================
The IPU6 driver communicates with firmware via the Syscom ABI. Syscom is an
inter-processor communication mechanism between the IPU scalar processors and
the CPU. There are a number of resources shared between firmware and software.
A system memory region where the message queues reside, firmware can access the
memory region via the IPU MMU. The Syscom queues are FIFO fixed depth queues
with a configurable number of tokens (messages). There are also common IPU6 MMIO
registers where the queue read and write indices reside. Software and firmware
function as producer and consumer of tokens in the queues and update the write
and read indices separately when sending or receiving each message.
The IPU6 driver must prepare and configure the number of input and output
queues, configure the count of tokens per queue and the size of per token before
initiating and starting the communication with firmware. Firmware and software
must use same configurations. The IPU6 Buttress has a number of firmware boot
parameter registers which can be used to store the address of configuration and
initialise the Syscom state, then driver can request firmware to start and run via
setting the scalar processor control status register.
Input System
137-142IPU6 Input System은 MIPI D-PHY와 여러 CSI-2 receiver로 구성됩니다. Camera sensor 또는 다른 MIPI CSI-2 output device에서 image pixel data를 capture하는 입력 경로입니다.
Input System
============
IPU6 input system consists of MIPI D-PHY and several CSI-2 receivers. It can
capture image pixel data from camera sensors or other MIPI CSI-2 output devices.
D-PHY와 CSI-2 port lane mapping
143-168IPU6는 SoC에 따라 서로 다른 D-PHY IP를 통합합니다. Tiger Lake와 Alder Lake는 MCD10 D-PHY를, Jasper Lake의 IPU6SE는 JSL D-PHY를, Meteor Lake의 IPU6EP는 Synopsys DWC D-PHY를 사용합니다.
D-PHY와 CSI-2 receiver controller 사이에는 port configuration, PHY wrapper 또는 D-PHY private test interface를 포함하는 adaptation layer가 있습니다. 세 D-PHY는 각각 `ipu6-isys-mcd-phy.c`, `ipu6-isys-jsl-phy.c`, `ipu6-isys-dwc-phy.c` driver가 program합니다.
Lane mapping도 version마다 다릅니다. Tiger Lake는 data lane 12개와 clock lane 8개로 최대 CSI-2 port 8개를 지원하며 자세한 PPI mapping은 `ipu6-isys-mcd-phy.c`에 있습니다. Jasper Lake와 Alder Lake는 data lane 8개와 clock lane 4개로 최대 port 4개를, Meteor Lake는 data lane 12개와 clock lane 6개로 최대 port 6개를 지원합니다.
CSI-2 port 두 개씩은 data lane을 공유하는 하나의 unit입니다. 예를 들어 port 0은 최대 data lane 4개, port 1은 최대 2개를 지원합니다. Port 0이 2 lane을 쓰면 port 1도 2 lane으로 함께 동작할 수 있지만, port 0이 4 lane을 모두 사용하면 공유 lane이 남지 않아 port 1을 사용할 수 없습니다. 같은 제약이 port pair 2/3, 4/5, 7/8에도 적용됩니다.
Port pair는 data lane을 공유하므로 각 port의 독립 최대치만으로 동시 사용 가능 여부를 판단하면 안 됩니다.
D-PHYs and CSI-2 ports lane mapping
-----------------------------------
The IPU6 integrates different D-PHY IPs on different SoCs, on Tiger Lake and
Alder Lake, IPU6 integrates MCD10 D-PHY, IPU6SE on Jasper Lake integrates JSL
D-PHY and IPU6EP on Meteor Lake integrates a Synopsys DWC D-PHY. There is an
adaptional layer between D-PHY and CSI-2 receiver controller which includes port
configuration, PHY wrapper or private test interfaces for D-PHY. There are 3
D-PHY drivers ``ipu6-isys-mcd-phy.c``, ``ipu6-isys-jsl-phy.c`` and
``ipu6-isys-dwc-phy.c`` program the above 3 D-PHYs in IPU6.
Different IPU6 versions have different D-PHY lanes mappings, On Tiger Lake,
there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports,
see the PPI mmapping in ``ipu6-isys-mcd-phy.c`` for more information. On Jasper
Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports
maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock
lanes so IPU6 support maximum 6 CSI-2 ports.
.. Note:: Each pair of CSI-2 two ports is a single unit that can share the data
lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support
maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2
port 0 with 2 data lanes can work together with CSI-2 port 1 with 2
data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1
will not be available as the 4 data lanes are shared by CSI-2 port 0
and 1. The same applies to CSI ports 2/3, 4/5 and 7/8.
ISYS firmware ABI
169-190IPU6 firmware는 software access를 위한 여러 ABI를 구현합니다. Software는 먼저 `struct ipu6_fw_isys_stream_cfg_data_abi` stream configuration을 준비하고 `STREAM_OPEN` command로 firmware에 전송합니다.
Stream configuration은 input pin과 output pin을 포함합니다. `struct ipu6_fw_isys_input_pin_info_abi`는 input source의 resolution과 data type을 정의하고, `struct ipu6_fw_isys_output_pin_info_abi`는 output resolution, stride, frame format 등을 정의합니다.
Stream open 성공을 나타내는 firmware interrupt를 받으면 driver는 `STREAM_START`와 `STREAM_CAPTURE` command를 보내 image frame capture를 시작합니다. `STREAM_CAPTURE`는 `struct ipu6_fw_isys_frame_buff_set`으로 buffer를 firmware에 queue합니다.
그 뒤 software는 firmware interrupt와 response를 기다립니다. `PIN_DATA_READY`는 특정 output pin의 buffer가 준비됐음을 뜻하며, software는 그 buffer를 user에게 반환할 수 있습니다. 실제 capture 절차는 :ref:`Examples<ipu6_isys_capture_examples>`를 참고합니다.
ISYS firmware ABIs
------------------
The IPU6 firmware implements a series of ABIs for software access. In general,
software firstly prepares the stream configuration ``struct
ipu6_fw_isys_stream_cfg_data_abi`` and sends the configuration to firmware via
sending ``STREAM_OPEN`` command. Stream configuration includes input pins and
output pins, input pin ``struct ipu6_fw_isys_input_pin_info_abi`` defines the
resolution and data type of input source, output pin ``struct
ipu6_fw_isys_output_pin_info_abi`` defines the output resolution, stride and
frame format, etc.
Once the driver gets the interrupt from firmware that indicates stream open
successfully, the driver will send the ``STREAM_START`` and ``STREAM_CAPTURE``
command to request firmware to start capturing image frames. ``STREAM_CAPTURE``
command queues the buffers to firmware with ``struct
ipu6_fw_isys_frame_buff_set``, software then waits for the interrupt and
response from firmware, ``PIN_DATA_READY`` means a buffer is ready on a specific
output pin and then software can return the buffer to user.
.. Note:: See :ref:`Examples<ipu6_isys_capture_examples>` about how to do
capture by IPU6 ISYS driver.
요약과 해설
ipu6.rst:1-190IPU6는 PCI 단일 function 안에서 ISYS와 PSYS를 운용하며 Buttress가 전원, interrupt, CSE 인증과 시간 동기화를 중재합니다. Driver는 자체 2단계 MMU와 DMA operation, CPD firmware loader, Syscom queue ABI를 구현하고 SoC별 D-PHY lane topology를 관리합니다.