요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
1
.. SPDX-License-Identifier: GPL-2.0
3
The cx2341x driver
4
==================
6
Memory at cx2341x chips
7
-----------------------
9
This section describes the cx2341x memory map and documents some of the
10
register space.
12
.. note:: the memory long words are little-endian ('intel format').
14
.. warning::
16
This information was figured out from searching through the memory
17
and registers, this information may not be correct and is certainly
18
not complete, and was not derived from anything more than searching
19
through the memory space with commands like:
21
.. code-block:: none
23
ivtvctl -O min=0x02000000,max=0x020000ff
25
So take this as is, I'm always searching for more stuff, it's a large
26
register space :-).
28
Memory Map
29
~~~~~~~~~~
31
The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
32
(Base Address Register 0). The addresses here are offsets relative to the
33
address held in BAR0.
35
.. code-block:: none
37
0x00000000-0x00ffffff Encoder memory space
38
0x00000000-0x0003ffff Encode.rom
39
???-??? MPEG buffer(s)
40
???-??? Raw video capture buffer(s)
41
???-??? Raw audio capture buffer(s)
42
???-??? Display buffers (6 or 9)
44
0x01000000-0x01ffffff Decoder memory space
45
0x01000000-0x0103ffff Decode.rom
46
???-??? MPEG buffers(s)
47
0x0114b000-0x0115afff Audio.rom (deprecated?)
49
0x02000000-0x0200ffff Register Space
51
Registers
52
~~~~~~~~~
54
The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
55
All of these registers are 32 bits wide.
57
.. code-block:: none
59
DMA Registers 0x000-0xff:
61
0x00 - Control:
62
0=reset/cancel, 1=read, 2=write, 4=stop
63
0x04 - DMA status:
64
1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error
65
0x08 - pci DMA pointer for read link list
66
0x0c - pci DMA pointer for write link list
67
0x10 - read/write DMA enable:
68
1=read enable, 2=write enable
69
0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes
70
0x18 - ??
71
0x1c - always 0x20 or 32, smaller values slow down DMA transactions
72
0x20 - always value of 0x780a010a
73
0x24-0x3c - usually just random values???
74
0x40 - Interrupt status
75
0x44 - Write a bit here and shows up in Interrupt status 0x40
76
0x48 - Interrupt Mask
77
0x4C - always value of 0xfffdffff,
78
if changed to 0xffffffff DMA write interrupts break.
79
0x50 - always 0xffffffff
80
0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are
81
3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the
82
interrupt masks???).
83
0x60-0x7C - random values
84
0x80 - first write linked list reg, for Encoder Memory addr
85
0x84 - first write linked list reg, for pci memory addr
86
0x88 - first write linked list reg, for length of buffer in memory addr
87
(|0x80000000 or this for last link)
88
0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
89
from linked list addr in reg 0x0c, firmware must push through or
90
something.
91
0xe0 - first (and only) read linked list reg, for pci memory addr
92
0xe4 - first (and only) read linked list reg, for Decoder memory addr
93
0xe8 - first (and only) read linked list reg, for length of buffer
94
0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
96
Memory locations for Encoder Buffers 0x700-0x7ff:
98
These registers show offsets of memory locations pertaining to each
99
buffer area used for encoding, have to shift them by <<1 first.
101
- 0x07F8: Encoder SDRAM refresh
102
- 0x07FC: Encoder SDRAM pre-charge
104
Memory locations for Decoder Buffers 0x800-0x8ff:
106
These registers show offsets of memory locations pertaining to each
107
buffer area used for decoding, have to shift them by <<1 first.
109
- 0x08F8: Decoder SDRAM refresh
110
- 0x08FC: Decoder SDRAM pre-charge
112
Other memory locations:
114
- 0x2800: Video Display Module control
115
- 0x2D00: AO (audio output?) control
116
- 0x2D24: Bytes Flushed
117
- 0x7000: LSB I2C write clock bit (inverted)
118
- 0x7004: LSB I2C write data bit (inverted)
119
- 0x7008: LSB I2C read clock bit
120
- 0x700c: LSB I2C read data bit
121
- 0x9008: GPIO get input state
122
- 0x900c: GPIO set output state
123
- 0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)
124
- 0x9050: SPU control
125
- 0x9054: Reset HW blocks
126
- 0x9058: VPU control
127
- 0xA018: Bit6: interrupt pending?
128
- 0xA064: APU command
131
Interrupt Status Register
132
~~~~~~~~~~~~~~~~~~~~~~~~~
134
The definition of the bits in the interrupt status register 0x0040, and the
135
interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to
136
execute.
138
- bit 31 Encoder Start Capture
139
- bit 30 Encoder EOS
140
- bit 29 Encoder VBI capture
141
- bit 28 Encoder Video Input Module reset event
142
- bit 27 Encoder DMA complete
143
- bit 24 Decoder audio mode change detection event (through event notification)
144
- bit 22 Decoder data request
145
- bit 20 Decoder DMA complete
146
- bit 19 Decoder VBI re-insertion
147
- bit 18 Decoder DMA err (linked-list bad)
149
Missing documentation
150
---------------------
152
- Encoder API post(?)
153
- Decoder API post(?)
154
- Decoder VTRACE event
157
The cx2341x firmware upload
158
---------------------------
160
This document describes how to upload the cx2341x firmware to the card.
162
How to find
163
~~~~~~~~~~~
165
See the web pages of the various projects that uses this chip for information
166
on how to obtain the firmware.
168
The firmware stored in a Windows driver can be detected as follows:
170
- Each firmware image is 256k bytes.
171
- The 1st 32-bit word of the Encoder image is 0x0000da7
172
- The 1st 32-bit word of the Decoder image is 0x00003a7
173
- The 2nd 32-bit word of both images is 0xaa55bb66
175
How to load
176
~~~~~~~~~~~
178
- Issue the FWapi command to stop the encoder if it is running. Wait for the
179
command to complete.
180
- Issue the FWapi command to stop the decoder if it is running. Wait for the
181
command to complete.
182
- Issue the I2C command to the digitizer to stop emitting VSYNC events.
183
- Issue the FWapi command to halt the encoder's firmware.
184
- Sleep for 10ms.
185
- Issue the FWapi command to halt the decoder's firmware.
186
- Sleep for 10ms.
187
- Write 0x00000000 to register 0x2800 to stop the Video Display Module.
188
- Write 0x00000005 to register 0x2D00 to stop the AO (audio output?).
189
- Write 0x00000000 to register 0xA064 to ping? the APU.
190
- Write 0xFFFFFFFE to register 0x9058 to stop the VPU.
191
- Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.
192
- Write 0x00000001 to register 0x9050 to stop the SPU.
193
- Sleep for 10ms.
194
- Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
195
- Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
196
- Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
197
- Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
198
- Sleep for 512ms. (600ms is recommended)
199
- Transfer the encoder's firmware image to offset 0 in Encoder memory space.
200
- Transfer the decoder's firmware image to offset 0 in Decoder memory space.
201
- Use a read-modify-write operation to Clear bit 0 of register 0x9050 to
202
re-enable the SPU.
203
- Sleep for 1 second.
204
- Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058
205
to re-enable the VPU.
206
- Sleep for 1 second.
207
- Issue status API commands to both firmware images to verify.
210
How to call the firmware API
211
----------------------------
213
The preferred calling convention is known as the firmware mailbox. The
214
mailboxes are basically a fixed length array that serves as the call-stack.
216
Firmware mailboxes can be located by searching the encoder and decoder memory
217
for a 16 byte signature. That signature will be located on a 256-byte boundary.
219
Signature:
221
.. code-block:: none
223
0x78, 0x56, 0x34, 0x12, 0x12, 0x78, 0x56, 0x34,
224
0x34, 0x12, 0x78, 0x56, 0x56, 0x34, 0x12, 0x78
226
The firmware implements 20 mailboxes of 20 32-bit words. The first 10 are
227
reserved for API calls. The second 10 are used by the firmware for event
228
notification.
230
====== =================
231
Index Name
232
====== =================
233
0 Flags
234
1 Command
235
2 Return value
236
3 Timeout
237
4-19 Parameter/Result
238
====== =================
241
The flags are defined in the following table. The direction is from the
242
perspective of the firmware.
244
==== ========== ============================================
245
Bit Direction Purpose
246
==== ========== ============================================
247
2 O Firmware has processed the command.
248
1 I Driver has finished setting the parameters.
249
0 I Driver is using this mailbox.
250
==== ========== ============================================
252
The command is a 32-bit enumerator. The API specifics may be found in this
253
chapter.
255
The return value is a 32-bit enumerator. Only two values are currently defined:
257
- 0=success
258
- -1=command undefined.
260
There are 16 parameters/results 32-bit fields. The driver populates these fields
261
with values for all the parameters required by the call. The driver overwrites
262
these fields with result values returned by the call.
264
The timeout value protects the card from a hung driver thread. If the driver
265
doesn't handle the completed call within the timeout specified, the firmware
266
will reset that mailbox.
268
To make an API call, the driver iterates over each mailbox looking for the
269
first one available (bit 0 has been cleared). The driver sets that bit, fills
270
in the command enumerator, the timeout value and any required parameters. The
271
driver then sets the parameter ready bit (bit 1). The firmware scans the
272
mailboxes for pending commands, processes them, sets the result code, populates
273
the result value array with that call's return values and sets the call
274
complete bit (bit 2). Once bit 2 is set, the driver should retrieve the results
275
and clear all the flags. If the driver does not perform this task within the
276
time set in the timeout register, the firmware will reset that mailbox.
278
Event notifications are sent from the firmware to the host. The host tells the
279
firmware which events it is interested in via an API call. That call tells the
280
firmware which notification mailbox to use. The firmware signals the host via
281
an interrupt. Only the 16 Results fields are used, the Flags, Command, Return
282
value and Timeout words are not used.
285
OSD firmware API description
286
----------------------------
288
.. note:: this API is part of the decoder firmware, so it's cx23415 only.
292
CX2341X_OSD_GET_FRAMEBUFFER
293
~~~~~~~~~~~~~~~~~~~~~~~~~~~
295
Enum: 65/0x41
297
Description
298
^^^^^^^^^^^
300
Return base and length of contiguous OSD memory.
302
Result[0]
303
^^^^^^^^^
305
OSD base address
307
Result[1]
308
^^^^^^^^^
310
OSD length
314
CX2341X_OSD_GET_PIXEL_FORMAT
315
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
317
Enum: 66/0x42
319
Description
320
^^^^^^^^^^^
322
Query OSD format
324
Result[0]
325
^^^^^^^^^
327
0=8bit index
328
1=16bit RGB 5:6:5
329
2=16bit ARGB 1:5:5:5
330
3=16bit ARGB 1:4:4:4
331
4=32bit ARGB 8:8:8:8
335
CX2341X_OSD_SET_PIXEL_FORMAT
336
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
338
Enum: 67/0x43
340
Description
341
^^^^^^^^^^^
343
Assign pixel format
345
Param[0]
346
^^^^^^^^
348
- 0=8bit index
349
- 1=16bit RGB 5:6:5
350
- 2=16bit ARGB 1:5:5:5
351
- 3=16bit ARGB 1:4:4:4
352
- 4=32bit ARGB 8:8:8:8
356
CX2341X_OSD_GET_STATE
357
~~~~~~~~~~~~~~~~~~~~~
359
Enum: 68/0x44
361
Description
362
^^^^^^^^^^^
364
Query OSD state
366
Result[0]
367
^^^^^^^^^
369
- Bit 0 0=off, 1=on
370
- Bits 1:2 alpha control
371
- Bits 3:5 pixel format
375
CX2341X_OSD_SET_STATE
376
~~~~~~~~~~~~~~~~~~~~~
378
Enum: 69/0x45
380
Description
381
^^^^^^^^^^^
383
OSD switch
385
Param[0]
386
^^^^^^^^
388
0=off, 1=on
392
CX2341X_OSD_GET_OSD_COORDS
393
~~~~~~~~~~~~~~~~~~~~~~~~~~
395
Enum: 70/0x46
397
Description
398
^^^^^^^^^^^
400
Retrieve coordinates of OSD area blended with video
402
Result[0]
403
^^^^^^^^^
405
OSD buffer address
407
Result[1]
408
^^^^^^^^^
410
Stride in pixels
412
Result[2]
413
^^^^^^^^^
415
Lines in OSD buffer
417
Result[3]
418
^^^^^^^^^
420
Horizontal offset in buffer
422
Result[4]
423
^^^^^^^^^
425
Vertical offset in buffer
429
CX2341X_OSD_SET_OSD_COORDS
430
~~~~~~~~~~~~~~~~~~~~~~~~~~
432
Enum: 71/0x47
434
Description
435
^^^^^^^^^^^
437
Assign the coordinates of the OSD area to blend with video
439
Param[0]
440
^^^^^^^^
442
buffer address
444
Param[1]
445
^^^^^^^^
447
buffer stride in pixels
449
Param[2]
450
^^^^^^^^
452
lines in buffer
454
Param[3]
455
^^^^^^^^
457
horizontal offset
459
Param[4]
460
^^^^^^^^
462
vertical offset
466
CX2341X_OSD_GET_SCREEN_COORDS
467
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
469
Enum: 72/0x48
471
Description
472
^^^^^^^^^^^
474
Retrieve OSD screen area coordinates
476
Result[0]
477
^^^^^^^^^
479
top left horizontal offset
481
Result[1]
482
^^^^^^^^^
484
top left vertical offset
486
Result[2]
487
^^^^^^^^^
489
bottom right horizontal offset
491
Result[3]
492
^^^^^^^^^
494
bottom right vertical offset
498
CX2341X_OSD_SET_SCREEN_COORDS
499
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
501
Enum: 73/0x49
503
Description
504
^^^^^^^^^^^
506
Assign the coordinates of the screen area to blend with video
508
Param[0]
509
^^^^^^^^
511
top left horizontal offset
513
Param[1]
514
^^^^^^^^
516
top left vertical offset
518
Param[2]
519
^^^^^^^^
521
bottom left horizontal offset
523
Param[3]
524
^^^^^^^^
526
bottom left vertical offset
530
CX2341X_OSD_GET_GLOBAL_ALPHA
531
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
533
Enum: 74/0x4A
535
Description
536
^^^^^^^^^^^
538
Retrieve OSD global alpha
540
Result[0]
541
^^^^^^^^^
543
global alpha: 0=off, 1=on
545
Result[1]
546
^^^^^^^^^
548
bits 0:7 global alpha
552
CX2341X_OSD_SET_GLOBAL_ALPHA
553
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
555
Enum: 75/0x4B
557
Description
558
^^^^^^^^^^^
560
Update global alpha
562
Param[0]
563
^^^^^^^^
565
global alpha: 0=off, 1=on
567
Param[1]
568
^^^^^^^^
570
global alpha (8 bits)
572
Param[2]
573
^^^^^^^^
575
local alpha: 0=on, 1=off
579
CX2341X_OSD_SET_BLEND_COORDS
580
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
582
Enum: 78/0x4C
584
Description
585
^^^^^^^^^^^
587
Move start of blending area within display buffer
589
Param[0]
590
^^^^^^^^
592
horizontal offset in buffer
594
Param[1]
595
^^^^^^^^
597
vertical offset in buffer
601
CX2341X_OSD_GET_FLICKER_STATE
602
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
604
Enum: 79/0x4F
606
Description
607
^^^^^^^^^^^
609
Retrieve flicker reduction module state
611
Result[0]
612
^^^^^^^^^
614
flicker state: 0=off, 1=on
618
CX2341X_OSD_SET_FLICKER_STATE
619
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
621
Enum: 80/0x50
623
Description
624
^^^^^^^^^^^
626
Set flicker reduction module state
628
Param[0]
629
^^^^^^^^
631
State: 0=off, 1=on
635
CX2341X_OSD_BLT_COPY
636
~~~~~~~~~~~~~~~~~~~~
638
Enum: 82/0x52
640
Description
641
^^^^^^^^^^^
643
BLT copy
645
Param[0]
646
^^^^^^^^
648
.. code-block:: none
650
'0000' zero
651
'0001' ~destination AND ~source
652
'0010' ~destination AND source
653
'0011' ~destination
654
'0100' destination AND ~source
655
'0101' ~source
656
'0110' destination XOR source
657
'0111' ~destination OR ~source
658
'1000' ~destination AND ~source
659
'1001' destination XNOR source
660
'1010' source
661
'1011' ~destination OR source
662
'1100' destination
663
'1101' destination OR ~source
664
'1110' destination OR source
665
'1111' one
668
Param[1]
669
^^^^^^^^
671
Resulting alpha blending
673
- '01' source_alpha
674
- '10' destination_alpha
675
- '11' source_alpha*destination_alpha+1
676
(zero if both source and destination alpha are zero)
678
Param[2]
679
^^^^^^^^
681
.. code-block:: none
683
'00' output_pixel = source_pixel
685
'01' if source_alpha=0:
686
output_pixel = destination_pixel
687
if 256 > source_alpha > 1:
688
output_pixel = ((source_alpha + 1)*source_pixel +
689
(255 - source_alpha)*destination_pixel)/256
691
'10' if destination_alpha=0:
692
output_pixel = source_pixel
693
if 255 > destination_alpha > 0:
694
output_pixel = ((255 - destination_alpha)*source_pixel +
695
(destination_alpha + 1)*destination_pixel)/256
697
'11' if source_alpha=0:
698
source_temp = 0
699
if source_alpha=255:
700
source_temp = source_pixel*256
701
if 255 > source_alpha > 0:
702
source_temp = source_pixel*(source_alpha + 1)
703
if destination_alpha=0:
704
destination_temp = 0
705
if destination_alpha=255:
706
destination_temp = destination_pixel*256
707
if 255 > destination_alpha > 0:
708
destination_temp = destination_pixel*(destination_alpha + 1)
709
output_pixel = (source_temp + destination_temp)/256
711
Param[3]
712
^^^^^^^^
714
width
716
Param[4]
717
^^^^^^^^
719
height
721
Param[5]
722
^^^^^^^^
724
destination pixel mask
726
Param[6]
727
^^^^^^^^
729
destination rectangle start address
731
Param[7]
732
^^^^^^^^
734
destination stride in dwords
736
Param[8]
737
^^^^^^^^
739
source stride in dwords
741
Param[9]
742
^^^^^^^^
744
source rectangle start address
748
CX2341X_OSD_BLT_FILL
749
~~~~~~~~~~~~~~~~~~~~
751
Enum: 83/0x53
753
Description
754
^^^^^^^^^^^
756
BLT fill color
758
Param[0]
759
^^^^^^^^
761
Same as Param[0] on API 0x52
763
Param[1]
764
^^^^^^^^
766
Same as Param[1] on API 0x52
768
Param[2]
769
^^^^^^^^
771
Same as Param[2] on API 0x52
773
Param[3]
774
^^^^^^^^
776
width
778
Param[4]
779
^^^^^^^^
781
height
783
Param[5]
784
^^^^^^^^
786
destination pixel mask
788
Param[6]
789
^^^^^^^^
791
destination rectangle start address
793
Param[7]
794
^^^^^^^^
796
destination stride in dwords
798
Param[8]
799
^^^^^^^^
801
color fill value
805
CX2341X_OSD_BLT_TEXT
806
~~~~~~~~~~~~~~~~~~~~
808
Enum: 84/0x54
810
Description
811
^^^^^^^^^^^
813
BLT for 8 bit alpha text source
815
Param[0]
816
^^^^^^^^
818
Same as Param[0] on API 0x52
820
Param[1]
821
^^^^^^^^
823
Same as Param[1] on API 0x52
825
Param[2]
826
^^^^^^^^
828
Same as Param[2] on API 0x52
830
Param[3]
831
^^^^^^^^
833
width
835
Param[4]
836
^^^^^^^^
838
height
840
Param[5]
841
^^^^^^^^
843
destination pixel mask
845
Param[6]
846
^^^^^^^^
848
destination rectangle start address
850
Param[7]
851
^^^^^^^^
853
destination stride in dwords
855
Param[8]
856
^^^^^^^^
858
source stride in dwords
860
Param[9]
861
^^^^^^^^
863
source rectangle start address
865
Param[10]
866
^^^^^^^^^
868
color fill value
872
CX2341X_OSD_SET_FRAMEBUFFER_WINDOW
873
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
875
Enum: 86/0x56
877
Description
878
^^^^^^^^^^^
880
Positions the main output window on the screen. The coordinates must be
881
such that the entire window fits on the screen.
883
Param[0]
884
^^^^^^^^
886
window width
888
Param[1]
889
^^^^^^^^
891
window height
893
Param[2]
894
^^^^^^^^
896
top left window corner horizontal offset
898
Param[3]
899
^^^^^^^^
901
top left window corner vertical offset
905
CX2341X_OSD_SET_CHROMA_KEY
906
~~~~~~~~~~~~~~~~~~~~~~~~~~
908
Enum: 96/0x60
910
Description
911
^^^^^^^^^^^
913
Chroma key switch and color
915
Param[0]
916
^^^^^^^^
918
state: 0=off, 1=on
920
Param[1]
921
^^^^^^^^
923
color
927
CX2341X_OSD_GET_ALPHA_CONTENT_INDEX
928
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
930
Enum: 97/0x61
932
Description
933
^^^^^^^^^^^
935
Retrieve alpha content index
937
Result[0]
938
^^^^^^^^^
940
alpha content index, Range 0:15
944
CX2341X_OSD_SET_ALPHA_CONTENT_INDEX
945
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
947
Enum: 98/0x62
949
Description
950
^^^^^^^^^^^
952
Assign alpha content index
954
Param[0]
955
^^^^^^^^
957
alpha content index, range 0:15
960
Encoder firmware API description
961
--------------------------------
963
CX2341X_ENC_PING_FW
964
~~~~~~~~~~~~~~~~~~~
966
Enum: 128/0x80
968
Description
969
^^^^^^^^^^^
971
Does nothing. Can be used to check if the firmware is responding.
975
CX2341X_ENC_START_CAPTURE
976
~~~~~~~~~~~~~~~~~~~~~~~~~
978
Enum: 129/0x81
980
Description
981
^^^^^^^^^^^
983
Commences the capture of video, audio and/or VBI data. All encoding
984
parameters must be initialized prior to this API call. Captures frames
985
continuously or until a predefined number of frames have been captured.
987
Param[0]
988
^^^^^^^^
990
Capture stream type:
992
- 0=MPEG
993
- 1=Raw
994
- 2=Raw passthrough
995
- 3=VBI
998
Param[1]
999
^^^^^^^^
1001
Bitmask:
1003
- Bit 0 when set, captures YUV
1004
- Bit 1 when set, captures PCM audio
1005
- Bit 2 when set, captures VBI (same as param[0]=3)
1006
- Bit 3 when set, the capture destination is the decoder
1007
(same as param[0]=2)
1008
- Bit 4 when set, the capture destination is the host
1010
.. note:: this parameter is only meaningful for RAW capture type.
1014
CX2341X_ENC_STOP_CAPTURE
1015
~~~~~~~~~~~~~~~~~~~~~~~~
1017
Enum: 130/0x82
1019
Description
1020
^^^^^^^^^^^
1022
Ends a capture in progress
1024
Param[0]
1025
^^^^^^^^
1027
- 0=stop at end of GOP (generates IRQ)
1028
- 1=stop immediate (no IRQ)
1030
Param[1]
1031
^^^^^^^^
1033
Stream type to stop, see param[0] of API 0x81
1035
Param[2]
1036
^^^^^^^^
1038
Subtype, see param[1] of API 0x81
1042
CX2341X_ENC_SET_AUDIO_ID
1043
~~~~~~~~~~~~~~~~~~~~~~~~
1045
Enum: 137/0x89
1047
Description
1048
^^^^^^^^^^^
1050
Assigns the transport stream ID of the encoded audio stream
1052
Param[0]
1053
^^^^^^^^
1055
Audio Stream ID
1059
CX2341X_ENC_SET_VIDEO_ID
1060
~~~~~~~~~~~~~~~~~~~~~~~~
1062
Enum: 139/0x8B
1064
Description
1065
^^^^^^^^^^^
1067
Set video transport stream ID
1069
Param[0]
1070
^^^^^^^^
1072
Video stream ID
1076
CX2341X_ENC_SET_PCR_ID
1077
~~~~~~~~~~~~~~~~~~~~~~
1079
Enum: 141/0x8D
1081
Description
1082
^^^^^^^^^^^
1084
Assigns the transport stream ID for PCR packets
1086
Param[0]
1087
^^^^^^^^
1089
PCR Stream ID
1093
CX2341X_ENC_SET_FRAME_RATE
1094
~~~~~~~~~~~~~~~~~~~~~~~~~~
1096
Enum: 143/0x8F
1098
Description
1099
^^^^^^^^^^^
1101
Set video frames per second. Change occurs at start of new GOP.
1103
Param[0]
1104
^^^^^^^^
1106
- 0=30fps
1107
- 1=25fps
1111
CX2341X_ENC_SET_FRAME_SIZE
1112
~~~~~~~~~~~~~~~~~~~~~~~~~~
1114
Enum: 145/0x91
1116
Description
1117
^^^^^^^^^^^
1119
Select video stream encoding resolution.
1121
Param[0]
1122
^^^^^^^^
1124
Height in lines. Default 480
1126
Param[1]
1127
^^^^^^^^
1129
Width in pixels. Default 720
1133
CX2341X_ENC_SET_BIT_RATE
1134
~~~~~~~~~~~~~~~~~~~~~~~~
1136
Enum: 149/0x95
1138
Description
1139
^^^^^^^^^^^
1141
Assign average video stream bitrate.
1143
Param[0]
1144
^^^^^^^^
1146
0=variable bitrate, 1=constant bitrate
1148
Param[1]
1149
^^^^^^^^
1151
bitrate in bits per second
1153
Param[2]
1154
^^^^^^^^
1156
peak bitrate in bits per second, divided by 400
1158
Param[3]
1159
^^^^^^^^
1161
Mux bitrate in bits per second, divided by 400. May be 0 (default).
1163
Param[4]
1164
^^^^^^^^
1166
Rate Control VBR Padding
1168
Param[5]
1169
^^^^^^^^
1171
VBV Buffer used by encoder
1173
.. note::
1175
#) Param\[3\] and Param\[4\] seem to be always 0
1176
#) Param\[5\] doesn't seem to be used.
1180
CX2341X_ENC_SET_GOP_PROPERTIES
1181
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1183
Enum: 151/0x97
1185
Description
1186
^^^^^^^^^^^
1188
Setup the GOP structure
1190
Param[0]
1191
^^^^^^^^
1193
GOP size (maximum is 34)
1195
Param[1]
1196
^^^^^^^^
1198
Number of B frames between the I and P frame, plus 1.
1199
For example: IBBPBBPBBPBB --> GOP size: 12, number of B frames: 2+1 = 3
1201
.. note::
1203
GOP size must be a multiple of (B-frames + 1).
1207
CX2341X_ENC_SET_ASPECT_RATIO
1208
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1210
Enum: 153/0x99
1212
Description
1213
^^^^^^^^^^^
1215
Sets the encoding aspect ratio. Changes in the aspect ratio take effect
1216
at the start of the next GOP.
1218
Param[0]
1219
^^^^^^^^
1221
- '0000' forbidden
1222
- '0001' 1:1 square
1223
- '0010' 4:3
1224
- '0011' 16:9
1225
- '0100' 2.21:1
1226
- '0101' to '1111' reserved
1230
CX2341X_ENC_SET_DNR_FILTER_MODE
1231
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1233
Enum: 155/0x9B
1235
Description
1236
^^^^^^^^^^^
1238
Assign Dynamic Noise Reduction operating mode
1240
Param[0]
1241
^^^^^^^^
1243
Bit0: Spatial filter, set=auto, clear=manual
1244
Bit1: Temporal filter, set=auto, clear=manual
1246
Param[1]
1247
^^^^^^^^
1249
Median filter:
1251
- 0=Disabled
1252
- 1=Horizontal
1253
- 2=Vertical
1254
- 3=Horiz/Vert
1255
- 4=Diagonal
1259
CX2341X_ENC_SET_DNR_FILTER_PROPS
1260
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1262
Enum: 157/0x9D
1264
Description
1265
^^^^^^^^^^^
1267
These Dynamic Noise Reduction filter values are only meaningful when
1268
the respective filter is set to "manual" (See API 0x9B)
1270
Param[0]
1271
^^^^^^^^
1273
Spatial filter: default 0, range 0:15
1275
Param[1]
1276
^^^^^^^^
1278
Temporal filter: default 0, range 0:31
1282
CX2341X_ENC_SET_CORING_LEVELS
1283
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1285
Enum: 159/0x9F
1287
Description
1288
^^^^^^^^^^^
1290
Assign Dynamic Noise Reduction median filter properties.
1292
Param[0]
1293
^^^^^^^^
1295
Threshold above which the luminance median filter is enabled.
1296
Default: 0, range 0:255
1298
Param[1]
1299
^^^^^^^^
1301
Threshold below which the luminance median filter is enabled.
1302
Default: 255, range 0:255
1304
Param[2]
1305
^^^^^^^^
1307
Threshold above which the chrominance median filter is enabled.
1308
Default: 0, range 0:255
1310
Param[3]
1311
^^^^^^^^
1313
Threshold below which the chrominance median filter is enabled.
1314
Default: 255, range 0:255
1318
CX2341X_ENC_SET_SPATIAL_FILTER_TYPE
1319
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1321
Enum: 161/0xA1
1323
Description
1324
^^^^^^^^^^^
1326
Assign spatial prefilter parameters
1328
Param[0]
1329
^^^^^^^^
1331
Luminance filter
1333
- 0=Off
1334
- 1=1D Horizontal
1335
- 2=1D Vertical
1336
- 3=2D H/V Separable (default)
1337
- 4=2D Symmetric non-separable
1339
Param[1]
1340
^^^^^^^^
1342
Chrominance filter
1344
- 0=Off
1345
- 1=1D Horizontal (default)
1349
CX2341X_ENC_SET_VBI_LINE
1350
~~~~~~~~~~~~~~~~~~~~~~~~
1352
Enum: 183/0xB7
1354
Description
1355
^^^^^^^^^^^
1357
Selects VBI line number.
1359
Param[0]
1360
^^^^^^^^
1362
- Bits 0:4 line number
1363
- Bit 31 0=top_field, 1=bottom_field
1364
- Bits 0:31 all set specifies "all lines"
1366
Param[1]
1367
^^^^^^^^
1369
VBI line information features: 0=disabled, 1=enabled
1371
Param[2]
1372
^^^^^^^^
1374
Slicing: 0=None, 1=Closed Caption
1375
Almost certainly not implemented. Set to 0.
1377
Param[3]
1378
^^^^^^^^
1380
Luminance samples in this line.
1381
Almost certainly not implemented. Set to 0.
1383
Param[4]
1384
^^^^^^^^
1386
Chrominance samples in this line
1387
Almost certainly not implemented. Set to 0.
1391
CX2341X_ENC_SET_STREAM_TYPE
1392
~~~~~~~~~~~~~~~~~~~~~~~~~~~
1394
Enum: 185/0xB9
1396
Description
1397
^^^^^^^^^^^
1399
Assign stream type
1401
.. note::
1403
Transport stream is not working in recent firmwares.
1404
And in older firmwares the timestamps in the TS seem to be
1405
unreliable.
1407
Param[0]
1408
^^^^^^^^
1410
- 0=Program stream
1411
- 1=Transport stream
1412
- 2=MPEG1 stream
1413
- 3=PES A/V stream
1414
- 5=PES Video stream
1415
- 7=PES Audio stream
1416
- 10=DVD stream
1417
- 11=VCD stream
1418
- 12=SVCD stream
1419
- 13=DVD_S1 stream
1420
- 14=DVD_S2 stream
1424
CX2341X_ENC_SET_OUTPUT_PORT
1425
~~~~~~~~~~~~~~~~~~~~~~~~~~~
1427
Enum: 187/0xBB
1429
Description
1430
^^^^^^^^^^^
1432
Assign stream output port. Normally 0 when the data is copied through
1433
the PCI bus (DMA), and 1 when the data is streamed to another chip
1434
(pvrusb and cx88-blackbird).
1436
Param[0]
1437
^^^^^^^^
1439
- 0=Memory (default)
1440
- 1=Streaming
1441
- 2=Serial
1443
Param[1]
1444
^^^^^^^^
1446
Unknown, but leaving this to 0 seems to work best. Indications are that
1447
this might have to do with USB support, although passing anything but 0
1448
only breaks things.
1452
CX2341X_ENC_SET_AUDIO_PROPERTIES
1453
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1455
Enum: 189/0xBD
1457
Description
1458
^^^^^^^^^^^
1460
Set audio stream properties, may be called while encoding is in progress.
1462
.. note::
1464
All bitfields are consistent with ISO11172 documentation except
1465
bits 2:3 which ISO docs define as:
1467
- '11' Layer I
1468
- '10' Layer II
1469
- '01' Layer III
1470
- '00' Undefined
1472
This discrepancy may indicate a possible error in the documentation.
1473
Testing indicated that only Layer II is actually working, and that
1474
the minimum bitrate should be 192 kbps.
1476
Param[0]
1477
^^^^^^^^
1479
Bitmask:
1481
.. code-block:: none
1483
0:1 '00' 44.1Khz
1484
'01' 48Khz
1485
'10' 32Khz
1486
'11' reserved
1488
2:3 '01'=Layer I
1489
'10'=Layer II
1491
4:7 Bitrate:
1492
Index | Layer I | Layer II
1493
------+-------------+------------
1494
'0000' | free format | free format
1495
'0001' | 32 kbit/s | 32 kbit/s
1496
'0010' | 64 kbit/s | 48 kbit/s
1497
'0011' | 96 kbit/s | 56 kbit/s
1498
'0100' | 128 kbit/s | 64 kbit/s
1499
'0101' | 160 kbit/s | 80 kbit/s
1500
'0110' | 192 kbit/s | 96 kbit/s
1501
'0111' | 224 kbit/s | 112 kbit/s
1502
'1000' | 256 kbit/s | 128 kbit/s
1503
'1001' | 288 kbit/s | 160 kbit/s
1504
'1010' | 320 kbit/s | 192 kbit/s
1505
'1011' | 352 kbit/s | 224 kbit/s
1506
'1100' | 384 kbit/s | 256 kbit/s
1507
'1101' | 416 kbit/s | 320 kbit/s
1508
'1110' | 448 kbit/s | 384 kbit/s
1510
.. note::
1512
For Layer II, not all combinations of total bitrate
1513
and mode are allowed. See ISO11172-3 3-Annex B,
1514
Table 3-B.2
1516
8:9 '00'=Stereo
1517
'01'=JointStereo
1518
'10'=Dual
1519
'11'=Mono
1521
.. note::
1523
The cx23415 cannot decode Joint Stereo properly.
1525
10:11 Mode Extension used in joint_stereo mode.
1526
In Layer I and II they indicate which subbands are in
1527
intensity_stereo. All other subbands are coded in stereo.
1528
'00' subbands 4-31 in intensity_stereo, bound==4
1529
'01' subbands 8-31 in intensity_stereo, bound==8
1530
'10' subbands 12-31 in intensity_stereo, bound==12
1531
'11' subbands 16-31 in intensity_stereo, bound==16
1533
12:13 Emphasis:
1534
'00' None
1535
'01' 50/15uS
1536
'10' reserved
1537
'11' CCITT J.17
1539
14 CRC:
1540
'0' off
1541
'1' on
1543
15 Copyright:
1544
'0' off
1545
'1' on
1547
16 Generation:
1548
'0' copy
1549
'1' original
1553
CX2341X_ENC_HALT_FW
1554
~~~~~~~~~~~~~~~~~~~
1556
Enum: 195/0xC3
1558
Description
1559
^^^^^^^^^^^
1561
The firmware is halted and no further API calls are serviced until the
1562
firmware is uploaded again.
1566
CX2341X_ENC_GET_VERSION
1567
~~~~~~~~~~~~~~~~~~~~~~~
1569
Enum: 196/0xC4
1571
Description
1572
^^^^^^^^^^^
1574
Returns the version of the encoder firmware.
1576
Result[0]
1577
^^^^^^^^^
1579
Version bitmask:
1580
- Bits 0:15 build
1581
- Bits 16:23 minor
1582
- Bits 24:31 major
1586
CX2341X_ENC_SET_GOP_CLOSURE
1587
~~~~~~~~~~~~~~~~~~~~~~~~~~~
1589
Enum: 197/0xC5
1591
Description
1592
^^^^^^^^^^^
1594
Assigns the GOP open/close property.
1596
Param[0]
1597
^^^^^^^^
1599
- 0=Open
1600
- 1=Closed
1604
CX2341X_ENC_GET_SEQ_END
1605
~~~~~~~~~~~~~~~~~~~~~~~
1607
Enum: 198/0xC6
1609
Description
1610
^^^^^^^^^^^
1612
Obtains the sequence end code of the encoder's buffer. When a capture
1613
is started a number of interrupts are still generated, the last of
1614
which will have Result[0] set to 1 and Result[1] will contain the size
1615
of the buffer.
1617
Result[0]
1618
^^^^^^^^^
1620
State of the transfer (1 if last buffer)
1622
Result[1]
1623
^^^^^^^^^
1625
If Result[0] is 1, this contains the size of the last buffer, undefined
1626
otherwise.
1630
CX2341X_ENC_SET_PGM_INDEX_INFO
1631
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1633
Enum: 199/0xC7
1635
Description
1636
^^^^^^^^^^^
1638
Sets the Program Index Information.
1639
The information is stored as follows:
1641
.. code-block:: c
1643
struct info {
1644
u32 length; // Length of this frame
1645
u32 offset_low; // Offset in the file of the
1646
u32 offset_high; // start of this frame
1647
u32 mask1; // Bits 0-2 are the type mask:
1648
// 1=I, 2=P, 4=B
1649
// 0=End of Program Index, other fields
1650
// are invalid.
1651
u32 pts; // The PTS of the frame
1652
u32 mask2; // Bit 0 is bit 32 of the pts.
1653
};
1654
u32 table_ptr;
1655
struct info index[400];
1657
The table_ptr is the encoder memory address in the table were
1658
*new* entries will be written.
1660
.. note:: This is a ringbuffer, so the table_ptr will wraparound.
1662
Param[0]
1663
^^^^^^^^
1665
Picture Mask:
1666
- 0=No index capture
1667
- 1=I frames
1668
- 3=I,P frames
1669
- 7=I,P,B frames
1671
(Seems to be ignored, it always indexes I, P and B frames)
1673
Param[1]
1674
^^^^^^^^
1676
Elements requested (up to 400)
1678
Result[0]
1679
^^^^^^^^^
1681
Offset in the encoder memory of the start of the table.
1683
Result[1]
1684
^^^^^^^^^
1686
Number of allocated elements up to a maximum of Param[1]
1690
CX2341X_ENC_SET_VBI_CONFIG
1691
~~~~~~~~~~~~~~~~~~~~~~~~~~
1693
Enum: 200/0xC8
1695
Description
1696
^^^^^^^^^^^
1698
Configure VBI settings
1700
Param[0]
1701
^^^^^^^^
1703
Bitmap:
1705
.. code-block:: none
1707
0 Mode '0' Sliced, '1' Raw
1708
1:3 Insertion:
1709
'000' insert in extension & user data
1710
'001' insert in private packets
1711
'010' separate stream and user data
1712
'111' separate stream and private data
1713
8:15 Stream ID (normally 0xBD)
1715
Param[1]
1716
^^^^^^^^
1718
Frames per interrupt (max 8). Only valid in raw mode.
1720
Param[2]
1721
^^^^^^^^
1723
Total raw VBI frames. Only valid in raw mode.
1725
Param[3]
1726
^^^^^^^^
1728
Start codes
1730
Param[4]
1731
^^^^^^^^
1733
Stop codes
1735
Param[5]
1736
^^^^^^^^
1738
Lines per frame
1740
Param[6]
1741
^^^^^^^^
1743
Byte per line
1745
Result[0]
1746
^^^^^^^^^
1748
Observed frames per interrupt in raw mode only. Rage 1 to Param[1]
1750
Result[1]
1751
^^^^^^^^^
1753
Observed number of frames in raw mode. Range 1 to Param[2]
1755
Result[2]
1756
^^^^^^^^^
1758
Memory offset to start or raw VBI data
1762
CX2341X_ENC_SET_DMA_BLOCK_SIZE
1763
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1765
Enum: 201/0xC9
1767
Description
1768
^^^^^^^^^^^
1770
Set DMA transfer block size
1772
Param[0]
1773
^^^^^^^^
1775
DMA transfer block size in bytes or frames. When unit is bytes,
1776
supported block sizes are 2^7, 2^8 and 2^9 bytes.
1778
Param[1]
1779
^^^^^^^^
1781
Unit: 0=bytes, 1=frames
1785
CX2341X_ENC_GET_PREV_DMA_INFO_MB_10
1786
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1788
Enum: 202/0xCA
1790
Description
1791
^^^^^^^^^^^
1793
Returns information on the previous DMA transfer in conjunction with
1794
bit 27 of the interrupt mask. Uses mailbox 10.
1796
Result[0]
1797
^^^^^^^^^
1799
Type of stream
1801
Result[1]
1802
^^^^^^^^^
1804
Address Offset
1806
Result[2]
1807
^^^^^^^^^
1809
Maximum size of transfer
1813
CX2341X_ENC_GET_PREV_DMA_INFO_MB_9
1814
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1816
Enum: 203/0xCB
1818
Description
1819
^^^^^^^^^^^
1821
Returns information on the previous DMA transfer in conjunction with
1822
bit 27 or 18 of the interrupt mask. Uses mailbox 9.
1824
Result[0]
1825
^^^^^^^^^
1827
Status bits:
1828
- 0 read completed
1829
- 1 write completed
1830
- 2 DMA read error
1831
- 3 DMA write error
1832
- 4 Scatter-Gather array error
1834
Result[1]
1835
^^^^^^^^^
1837
DMA type
1839
Result[2]
1840
^^^^^^^^^
1842
Presentation Time Stamp bits 0..31
1844
Result[3]
1845
^^^^^^^^^
1847
Presentation Time Stamp bit 32
1851
CX2341X_ENC_SCHED_DMA_TO_HOST
1852
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1854
Enum: 204/0xCC
1856
Description
1857
^^^^^^^^^^^
1859
Setup DMA to host operation
1861
Param[0]
1862
^^^^^^^^
1864
Memory address of link list
1866
Param[1]
1867
^^^^^^^^
1869
Length of link list (wtf: what units ???)
1871
Param[2]
1872
^^^^^^^^
1874
DMA type (0=MPEG)
1878
CX2341X_ENC_INITIALIZE_INPUT
1879
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1881
Enum: 205/0xCD
1883
Description
1884
^^^^^^^^^^^
1886
Initializes the video input
1890
CX2341X_ENC_SET_FRAME_DROP_RATE
1891
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1893
Enum: 208/0xD0
1895
Description
1896
^^^^^^^^^^^
1898
For each frame captured, skip specified number of frames.
1900
Param[0]
1901
^^^^^^^^
1903
Number of frames to skip
1907
CX2341X_ENC_PAUSE_ENCODER
1908
~~~~~~~~~~~~~~~~~~~~~~~~~
1910
Enum: 210/0xD2
1912
Description
1913
^^^^^^^^^^^
1915
During a pause condition, all frames are dropped instead of being encoded.
1917
Param[0]
1918
^^^^^^^^
1920
- 0=Pause encoding
1921
- 1=Continue encoding
1925
CX2341X_ENC_REFRESH_INPUT
1926
~~~~~~~~~~~~~~~~~~~~~~~~~
1928
Enum: 211/0xD3
1930
Description
1931
^^^^^^^^^^^
1933
Refreshes the video input
1937
CX2341X_ENC_SET_COPYRIGHT
1938
~~~~~~~~~~~~~~~~~~~~~~~~~
1940
Enum: 212/0xD4
1942
Description
1943
^^^^^^^^^^^
1945
Sets stream copyright property
1947
Param[0]
1948
^^^^^^^^
1951
- 0=Stream is not copyrighted
1952
- 1=Stream is copyrighted
1956
CX2341X_ENC_SET_EVENT_NOTIFICATION
1957
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1959
Enum: 213/0xD5
1961
Description
1962
^^^^^^^^^^^
1964
Setup firmware to notify the host about a particular event. Host must
1965
unmask the interrupt bit.
1967
Param[0]
1968
^^^^^^^^
1970
Event (0=refresh encoder input)
1972
Param[1]
1973
^^^^^^^^
1975
Notification 0=disabled 1=enabled
1977
Param[2]
1978
^^^^^^^^
1980
Interrupt bit
1982
Param[3]
1983
^^^^^^^^
1985
Mailbox slot, -1 if no mailbox required.
1989
CX2341X_ENC_SET_NUM_VSYNC_LINES
1990
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1992
Enum: 214/0xD6
1994
Description
1995
^^^^^^^^^^^
1997
Depending on the analog video decoder used, this assigns the number
1998
of lines for field 1 and 2.
2000
Param[0]
2001
^^^^^^^^
2003
Field 1 number of lines:
2004
- 0x00EF for SAA7114
2005
- 0x00F0 for SAA7115
2006
- 0x0105 for Micronas
2008
Param[1]
2009
^^^^^^^^
2011
Field 2 number of lines:
2012
- 0x00EF for SAA7114
2013
- 0x00F0 for SAA7115
2014
- 0x0106 for Micronas
2018
CX2341X_ENC_SET_PLACEHOLDER
2019
~~~~~~~~~~~~~~~~~~~~~~~~~~~
2021
Enum: 215/0xD7
2023
Description
2024
^^^^^^^^^^^
2026
Provides a mechanism of inserting custom user data in the MPEG stream.
2028
Param[0]
2029
^^^^^^^^
2031
- 0=extension & user data
2032
- 1=private packet with stream ID 0xBD
2034
Param[1]
2035
^^^^^^^^
2037
Rate at which to insert data, in units of frames (for private packet)
2038
or GOPs (for ext. & user data)
2040
Param[2]
2041
^^^^^^^^
2043
Number of data DWORDs (below) to insert
2045
Param[3]
2046
^^^^^^^^
2048
Custom data 0
2050
Param[4]
2051
^^^^^^^^
2053
Custom data 1
2055
Param[5]
2056
^^^^^^^^
2058
Custom data 2
2060
Param[6]
2061
^^^^^^^^
2063
Custom data 3
2065
Param[7]
2066
^^^^^^^^
2068
Custom data 4
2070
Param[8]
2071
^^^^^^^^
2073
Custom data 5
2075
Param[9]
2076
^^^^^^^^
2078
Custom data 6
2080
Param[10]
2081
^^^^^^^^^
2083
Custom data 7
2085
Param[11]
2086
^^^^^^^^^
2088
Custom data 8
2092
CX2341X_ENC_MUTE_VIDEO
2093
~~~~~~~~~~~~~~~~~~~~~~
2095
Enum: 217/0xD9
2097
Description
2098
^^^^^^^^^^^
2100
Video muting
2102
Param[0]
2103
^^^^^^^^
2105
Bit usage:
2107
.. code-block:: none
2109
0 '0'=video not muted
2110
'1'=video muted, creates frames with the YUV color defined below
2111
1:7 Unused
2112
8:15 V chrominance information
2113
16:23 U chrominance information
2114
24:31 Y luminance information
2118
CX2341X_ENC_MUTE_AUDIO
2119
~~~~~~~~~~~~~~~~~~~~~~
2121
Enum: 218/0xDA
2123
Description
2124
^^^^^^^^^^^
2126
Audio muting
2128
Param[0]
2129
^^^^^^^^
2131
- 0=audio not muted
2132
- 1=audio muted (produces silent mpeg audio stream)
2136
CX2341X_ENC_SET_VERT_CROP_LINE
2137
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2139
Enum: 219/0xDB
2141
Description
2142
^^^^^^^^^^^
2144
Something to do with 'Vertical Crop Line'
2146
Param[0]
2147
^^^^^^^^
2149
If saa7114 and raw VBI capture and 60 Hz, then set to 10001.
2150
Else 0.
2154
CX2341X_ENC_MISC
2155
~~~~~~~~~~~~~~~~
2157
Enum: 220/0xDC
2159
Description
2160
^^^^^^^^^^^
2162
Miscellaneous actions. Not known for 100% what it does. It's really a
2163
sort of ioctl call. The first parameter is a command number, the second
2164
the value.
2166
Param[0]
2167
^^^^^^^^
2169
Command number:
2171
.. code-block:: none
2173
1=set initial SCR value when starting encoding (works).
2174
2=set quality mode (apparently some test setting).
2175
3=setup advanced VIM protection handling.
2176
Always 1 for the cx23416 and 0 for cx23415.
2177
4=generate DVD compatible PTS timestamps
2178
5=USB flush mode
2179
6=something to do with the quantization matrix
2180
7=set navigation pack insertion for DVD: adds 0xbf (private stream 2)
2181
packets to the MPEG. The size of these packets is 2048 bytes (including
2182
the header of 6 bytes: 0x000001bf + length). The payload is zeroed and
2183
it is up to the application to fill them in. These packets are apparently
2184
inserted every four frames.
2185
8=enable scene change detection (seems to be a failure)
2186
9=set history parameters of the video input module
2187
10=set input field order of VIM
2188
11=set quantization matrix
2189
12=reset audio interface after channel change or input switch (has no argument).
2190
Needed for the cx2584x, not needed for the mspx4xx, but it doesn't seem to
2191
do any harm calling it regardless.
2192
13=set audio volume delay
2193
14=set audio delay
2196
Param[1]
2197
^^^^^^^^
2199
Command value.
2201
Decoder firmware API description
2202
--------------------------------
2204
.. note:: this API is part of the decoder firmware, so it's cx23415 only.
2208
CX2341X_DEC_PING_FW
2209
~~~~~~~~~~~~~~~~~~~
2211
Enum: 0/0x00
2213
Description
2214
^^^^^^^^^^^
2216
This API call does nothing. It may be used to check if the firmware
2217
is responding.
2221
CX2341X_DEC_START_PLAYBACK
2222
~~~~~~~~~~~~~~~~~~~~~~~~~~
2224
Enum: 1/0x01
2226
Description
2227
^^^^^^^^^^^
2229
Begin or resume playback.
2231
Param[0]
2232
^^^^^^^^
2234
0 based frame number in GOP to begin playback from.
2236
Param[1]
2237
^^^^^^^^
2239
Specifies the number of muted audio frames to play before normal
2240
audio resumes. (This is not implemented in the firmware, leave at 0)
2244
CX2341X_DEC_STOP_PLAYBACK
2245
~~~~~~~~~~~~~~~~~~~~~~~~~
2247
Enum: 2/0x02
2249
Description
2250
^^^^^^^^^^^
2252
Ends playback and clears all decoder buffers. If PTS is not zero,
2253
playback stops at specified PTS.
2255
Param[0]
2256
^^^^^^^^
2258
Display 0=last frame, 1=black
2260
.. note::
2262
this takes effect immediately, so if you want to wait for a PTS,
2263
then use '0', otherwise the screen goes to black at once.
2264
You can call this later (even if there is no playback) with a 1 value
2265
to set the screen to black.
2267
Param[1]
2268
^^^^^^^^
2270
PTS low
2272
Param[2]
2273
^^^^^^^^
2275
PTS high
2279
CX2341X_DEC_SET_PLAYBACK_SPEED
2280
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2282
Enum: 3/0x03
2284
Description
2285
^^^^^^^^^^^
2287
Playback stream at speed other than normal. There are two modes of
2288
operation:
2290
- Smooth: host transfers entire stream and firmware drops unused
2291
frames.
2292
- Coarse: host drops frames based on indexing as required to achieve
2293
desired speed.
2295
Param[0]
2296
^^^^^^^^
2298
.. code-block:: none
2300
Bitmap:
2301
0:7 0 normal
2302
1 fast only "1.5 times"
2303
n nX fast, 1/nX slow
2304
30 Framedrop:
2305
'0' during 1.5 times play, every other B frame is dropped
2306
'1' during 1.5 times play, stream is unchanged (bitrate
2307
must not exceed 8mbps)
2308
31 Speed:
2309
'0' slow
2310
'1' fast
2312
.. note::
2314
n is limited to 2. Anything higher does not result in
2315
faster playback. Instead the host should start dropping frames.
2317
Param[1]
2318
^^^^^^^^
2320
Direction: 0=forward, 1=reverse
2322
.. note::
2324
to make reverse playback work you have to write full GOPs in
2325
reverse order.
2327
Param[2]
2328
^^^^^^^^
2330
.. code-block:: none
2332
Picture mask:
2333
1=I frames
2334
3=I, P frames
2335
7=I, P, B frames
2337
Param[3]
2338
^^^^^^^^
2340
B frames per GOP (for reverse play only)
2342
.. note::
2344
for reverse playback the Picture Mask should be set to I or I, P.
2345
Adding B frames to the mask will result in corrupt video. This field
2346
has to be set to the correct value in order to keep the timing correct.
2348
Param[4]
2349
^^^^^^^^
2351
Mute audio: 0=disable, 1=enable
2353
Param[5]
2354
^^^^^^^^
2356
Display 0=frame, 1=field
2358
Param[6]
2359
^^^^^^^^
2361
Specifies the number of muted audio frames to play before normal audio
2362
resumes. (Not implemented in the firmware, leave at 0)
2366
CX2341X_DEC_STEP_VIDEO
2367
~~~~~~~~~~~~~~~~~~~~~~
2369
Enum: 5/0x05
2371
Description
2372
^^^^^^^^^^^
2374
Each call to this API steps the playback to the next unit defined below
2375
in the current playback direction.
2377
Param[0]
2378
^^^^^^^^
2380
0=frame, 1=top field, 2=bottom field
2384
CX2341X_DEC_SET_DMA_BLOCK_SIZE
2385
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2387
Enum: 8/0x08
2389
Description
2390
^^^^^^^^^^^
2392
Set DMA transfer block size. Counterpart to API 0xC9
2394
Param[0]
2395
^^^^^^^^
2397
DMA transfer block size in bytes. A different size may be specified
2398
when issuing the DMA transfer command.
2402
CX2341X_DEC_GET_XFER_INFO
2403
~~~~~~~~~~~~~~~~~~~~~~~~~
2405
Enum: 9/0x09
2407
Description
2408
^^^^^^^^^^^
2410
This API call may be used to detect an end of stream condition.
2412
Result[0]
2413
^^^^^^^^^
2415
Stream type
2417
Result[1]
2418
^^^^^^^^^
2420
Address offset
2422
Result[2]
2423
^^^^^^^^^
2425
Maximum bytes to transfer
2427
Result[3]
2428
^^^^^^^^^
2430
Buffer fullness
2434
CX2341X_DEC_GET_DMA_STATUS
2435
~~~~~~~~~~~~~~~~~~~~~~~~~~
2437
Enum: 10/0x0A
2439
Description
2440
^^^^^^^^^^^
2442
Status of the last DMA transfer
2444
Result[0]
2445
^^^^^^^^^
2447
Bit 1 set means transfer complete
2448
Bit 2 set means DMA error
2449
Bit 3 set means linked list error
2451
Result[1]
2452
^^^^^^^^^
2454
DMA type: 0=MPEG, 1=OSD, 2=YUV
2458
CX2341X_DEC_SCHED_DMA_FROM_HOST
2459
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2461
Enum: 11/0x0B
2463
Description
2464
^^^^^^^^^^^
2466
Setup DMA from host operation. Counterpart to API 0xCC
2468
Param[0]
2469
^^^^^^^^
2471
Memory address of link list
2473
Param[1]
2474
^^^^^^^^
2476
Total # of bytes to transfer
2478
Param[2]
2479
^^^^^^^^
2481
DMA type (0=MPEG, 1=OSD, 2=YUV)
2485
CX2341X_DEC_PAUSE_PLAYBACK
2486
~~~~~~~~~~~~~~~~~~~~~~~~~~
2488
Enum: 13/0x0D
2490
Description
2491
^^^^^^^^^^^
2493
Freeze playback immediately. In this mode, when internal buffers are
2494
full, no more data will be accepted and data request IRQs will be
2495
masked.
2497
Param[0]
2498
^^^^^^^^
2500
Display: 0=last frame, 1=black
2504
CX2341X_DEC_HALT_FW
2505
~~~~~~~~~~~~~~~~~~~
2507
Enum: 14/0x0E
2509
Description
2510
^^^^^^^^^^^
2512
The firmware is halted and no further API calls are serviced until
2513
the firmware is uploaded again.
2517
CX2341X_DEC_SET_STANDARD
2518
~~~~~~~~~~~~~~~~~~~~~~~~
2520
Enum: 16/0x10
2522
Description
2523
^^^^^^^^^^^
2525
Selects display standard
2527
Param[0]
2528
^^^^^^^^
2530
0=NTSC, 1=PAL
2534
CX2341X_DEC_GET_VERSION
2535
~~~~~~~~~~~~~~~~~~~~~~~
2537
Enum: 17/0x11
2539
Description
2540
^^^^^^^^^^^
2542
Returns decoder firmware version information
2544
Result[0]
2545
^^^^^^^^^
2547
Version bitmask:
2548
- Bits 0:15 build
2549
- Bits 16:23 minor
2550
- Bits 24:31 major
2554
CX2341X_DEC_SET_STREAM_INPUT
2555
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2557
Enum: 20/0x14
2559
Description
2560
^^^^^^^^^^^
2562
Select decoder stream input port
2564
Param[0]
2565
^^^^^^^^
2567
0=memory (default), 1=streaming
2571
CX2341X_DEC_GET_TIMING_INFO
2572
~~~~~~~~~~~~~~~~~~~~~~~~~~~
2574
Enum: 21/0x15
2576
Description
2577
^^^^^^^^^^^
2579
Returns timing information from start of playback
2581
Result[0]
2582
^^^^^^^^^
2584
Frame count by decode order
2586
Result[1]
2587
^^^^^^^^^
2589
Video PTS bits 0:31 by display order
2591
Result[2]
2592
^^^^^^^^^
2594
Video PTS bit 32 by display order
2596
Result[3]
2597
^^^^^^^^^
2599
SCR bits 0:31 by display order
2601
Result[4]
2602
^^^^^^^^^
2604
SCR bit 32 by display order
2608
CX2341X_DEC_SET_AUDIO_MODE
2609
~~~~~~~~~~~~~~~~~~~~~~~~~~
2611
Enum: 22/0x16
2613
Description
2614
^^^^^^^^^^^
2616
Select audio mode
2618
Param[0]
2619
^^^^^^^^
2621
Dual mono mode action
2622
0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
2624
Param[1]
2625
^^^^^^^^
2627
Stereo mode action:
2628
0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
2632
CX2341X_DEC_SET_EVENT_NOTIFICATION
2633
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2635
Enum: 23/0x17
2637
Description
2638
^^^^^^^^^^^
2640
Setup firmware to notify the host about a particular event.
2641
Counterpart to API 0xD5
2643
Param[0]
2644
^^^^^^^^
2646
Event:
2647
- 0=Audio mode change between mono, (joint) stereo and dual channel.
2648
- 3=Decoder started
2649
- 4=Unknown: goes off 10-15 times per second while decoding.
2650
- 5=Some sync event: goes off once per frame.
2652
Param[1]
2653
^^^^^^^^
2655
Notification 0=disabled, 1=enabled
2657
Param[2]
2658
^^^^^^^^
2660
Interrupt bit
2662
Param[3]
2663
^^^^^^^^
2665
Mailbox slot, -1 if no mailbox required.
2669
CX2341X_DEC_SET_DISPLAY_BUFFERS
2670
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2672
Enum: 24/0x18
2674
Description
2675
^^^^^^^^^^^
2677
Number of display buffers. To decode all frames in reverse playback you
2678
must use nine buffers.
2680
Param[0]
2681
^^^^^^^^
2683
0=six buffers, 1=nine buffers
2687
CX2341X_DEC_EXTRACT_VBI
2688
~~~~~~~~~~~~~~~~~~~~~~~
2690
Enum: 25/0x19
2692
Description
2693
^^^^^^^^^^^
2695
Extracts VBI data
2697
Param[0]
2698
^^^^^^^^
2700
0=extract from extension & user data, 1=extract from private packets
2702
Result[0]
2703
^^^^^^^^^
2705
VBI table location
2707
Result[1]
2708
^^^^^^^^^
2710
VBI table size
2714
CX2341X_DEC_SET_DECODER_SOURCE
2715
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2717
Enum: 26/0x1A
2719
Description
2720
^^^^^^^^^^^
2722
Selects decoder source. Ensure that the parameters passed to this
2723
API match the encoder settings.
2725
Param[0]
2726
^^^^^^^^
2728
Mode: 0=MPEG from host, 1=YUV from encoder, 2=YUV from host
2730
Param[1]
2731
^^^^^^^^
2733
YUV picture width
2735
Param[2]
2736
^^^^^^^^
2738
YUV picture height
2740
Param[3]
2741
^^^^^^^^
2743
Bitmap: see Param[0] of API 0xBD
2747
CX2341X_DEC_SET_PREBUFFERING
2748
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2750
Enum: 30/0x1E
2752
Description
2753
^^^^^^^^^^^
2755
Decoder prebuffering, when enabled up to 128KB are buffered for
2756
streams <8mpbs or 640KB for streams >8mbps
2758
Param[0]
2759
^^^^^^^^
2761
0=off, 1=on
2763
PVR350 Video decoder registers 0x02002800 -> 0x02002B00
2764
-------------------------------------------------------
2766
Author: Ian Armstrong <ian@iarmst.demon.co.uk>
2768
Version: v0.4
2770
Date: 12 March 2007
2773
This list has been worked out through trial and error. There will be mistakes
2774
and omissions. Some registers have no obvious effect so it's hard to say what
2775
they do, while others interact with each other, or require a certain load
2776
sequence. Horizontal filter setup is one example, with six registers working
2777
in unison and requiring a certain load sequence to correctly configure. The
2778
indexed colour palette is much easier to set at just two registers, but again
2779
it requires a certain load sequence.
2781
Some registers are fussy about what they are set to. Load in a bad value & the
2782
decoder will fail. A firmware reload will often recover, but sometimes a reset
2783
is required. For registers containing size information, setting them to 0 is
2784
generally a bad idea. For other control registers i.e. 2878, you'll only find
2785
out what values are bad when it hangs.
2787
.. code-block:: none
2789
--------------------------------------------------------------------------------
2790
2800
2791
bit 0
2792
Decoder enable
2793
0 = disable
2794
1 = enable
2795
--------------------------------------------------------------------------------
2796
2804
2797
bits 0:31
2798
Decoder horizontal Y alias register 1
2799
---------------
2800
2808
2801
bits 0:31
2802
Decoder horizontal Y alias register 2
2803
---------------
2804
280C
2805
bits 0:31
2806
Decoder horizontal Y alias register 3
2807
---------------
2808
2810
2809
bits 0:31
2810
Decoder horizontal Y alias register 4
2811
---------------
2812
2814
2813
bits 0:31
2814
Decoder horizontal Y alias register 5
2815
---------------
2816
2818
2817
bits 0:31
2818
Decoder horizontal Y alias trigger
2820
These six registers control the horizontal aliasing filter for the Y plane.
2821
The first five registers must all be loaded before accessing the trigger
2822
(2818), as this register actually clocks the data through for the first
2823
five.
2825
To correctly program set the filter, this whole procedure must be done 16
2826
times. The actual register contents are copied from a lookup-table in the
2827
firmware which contains 4 different filter settings.
2829
--------------------------------------------------------------------------------
2830
281C
2831
bits 0:31
2832
Decoder horizontal UV alias register 1
2833
---------------
2834
2820
2835
bits 0:31
2836
Decoder horizontal UV alias register 2
2837
---------------
2838
2824
2839
bits 0:31
2840
Decoder horizontal UV alias register 3
2841
---------------
2842
2828
2843
bits 0:31
2844
Decoder horizontal UV alias register 4
2845
---------------
2846
282C
2847
bits 0:31
2848
Decoder horizontal UV alias register 5
2849
---------------
2850
2830
2851
bits 0:31
2852
Decoder horizontal UV alias trigger
2854
These six registers control the horizontal aliasing for the UV plane.
2855
Operation is the same as the Y filter, with 2830 being the trigger
2856
register.
2858
--------------------------------------------------------------------------------
2859
2834
2860
bits 0:15
2861
Decoder Y source width in pixels
2863
bits 16:31
2864
Decoder Y destination width in pixels
2865
---------------
2866
2838
2867
bits 0:15
2868
Decoder UV source width in pixels
2870
bits 16:31
2871
Decoder UV destination width in pixels
2873
NOTE: For both registers, the resulting image must be fully visible on
2874
screen. If the image exceeds the right edge both the source and destination
2875
size must be adjusted to reflect the visible portion. For the source width,
2876
you must take into account the scaling when calculating the new value.
2877
--------------------------------------------------------------------------------
2879
283C
2880
bits 0:31
2881
Decoder Y horizontal scaling
2882
Normally = Reg 2854 >> 2
2883
---------------
2884
2840
2885
bits 0:31
2886
Decoder ?? unknown - horizontal scaling
2887
Usually 0x00080514
2888
---------------
2889
2844
2890
bits 0:31
2891
Decoder UV horizontal scaling
2892
Normally = Reg 2854 >> 2
2893
---------------
2894
2848
2895
bits 0:31
2896
Decoder ?? unknown - horizontal scaling
2897
Usually 0x00100514
2898
---------------
2899
284C
2900
bits 0:31
2901
Decoder ?? unknown - Y plane
2902
Usually 0x00200020
2903
---------------
2904
2850
2905
bits 0:31
2906
Decoder ?? unknown - UV plane
2907
Usually 0x00200020
2908
---------------
2909
2854
2910
bits 0:31
2911
Decoder 'master' value for horizontal scaling
2912
---------------
2913
2858
2914
bits 0:31
2915
Decoder ?? unknown
2916
Usually 0
2917
---------------
2918
285C
2919
bits 0:31
2920
Decoder ?? unknown
2921
Normally = Reg 2854 >> 1
2922
---------------
2923
2860
2924
bits 0:31
2925
Decoder ?? unknown
2926
Usually 0
2927
---------------
2928
2864
2929
bits 0:31
2930
Decoder ?? unknown
2931
Normally = Reg 2854 >> 1
2932
---------------
2933
2868
2934
bits 0:31
2935
Decoder ?? unknown
2936
Usually 0
2938
Most of these registers either control horizontal scaling, or appear linked
2939
to it in some way. Register 2854 contains the 'master' value & the other
2940
registers can be calculated from that one. You must also remember to
2941
correctly set the divider in Reg 2874.
2943
To enlarge:
2944
Reg 2854 = (source_width * 0x00200000) / destination_width
2945
Reg 2874 = No divide
2947
To reduce from full size down to half size:
2948
Reg 2854 = (source_width/2 * 0x00200000) / destination width
2949
Reg 2874 = Divide by 2
2951
To reduce from half size down to quarter size:
2952
Reg 2854 = (source_width/4 * 0x00200000) / destination width
2953
Reg 2874 = Divide by 4
2955
The result is always rounded up.
2957
--------------------------------------------------------------------------------
2958
286C
2959
bits 0:15
2960
Decoder horizontal Y buffer offset
2962
bits 15:31
2963
Decoder horizontal UV buffer offset
2965
Offset into the video image buffer. If the offset is gradually incremented,
2966
the on screen image will move left & wrap around higher up on the right.
2968
--------------------------------------------------------------------------------
2969
2870
2970
bits 0:15
2971
Decoder horizontal Y output offset
2973
bits 16:31
2974
Decoder horizontal UV output offset
2976
Offsets the actual video output. Controls output alignment of the Y & UV
2977
planes. The higher the value, the greater the shift to the left. Use
2978
reg 2890 to move the image right.
2980
--------------------------------------------------------------------------------
2981
2874
2982
bits 0:1
2983
Decoder horizontal Y output size divider
2984
00 = No divide
2985
01 = Divide by 2
2986
10 = Divide by 3
2988
bits 4:5
2989
Decoder horizontal UV output size divider
2990
00 = No divide
2991
01 = Divide by 2
2992
10 = Divide by 3
2994
bit 8
2995
Decoder ?? unknown
2996
0 = Normal
2997
1 = Affects video output levels
2999
bit 16
3000
Decoder ?? unknown
3001
0 = Normal
3002
1 = Disable horizontal filter
3004
--------------------------------------------------------------------------------
3005
2878
3006
bit 0
3007
?? unknown
3009
bit 1
3010
osd on/off
3011
0 = osd off
3012
1 = osd on
3014
bit 2
3015
Decoder + osd video timing
3016
0 = NTSC
3017
1 = PAL
3019
bits 3:4
3020
?? unknown
3022
bit 5
3023
Decoder + osd
3024
Swaps upper & lower fields
3026
--------------------------------------------------------------------------------
3027
287C
3028
bits 0:10
3029
Decoder & osd ?? unknown
3030
Moves entire screen horizontally. Starts at 0x005 with the screen
3031
shifted heavily to the right. Incrementing in steps of 0x004 will
3032
gradually shift the screen to the left.
3034
bits 11:31
3035
?? unknown
3037
Normally contents are 0x00101111 (NTSC) or 0x1010111d (PAL)
3039
--------------------------------------------------------------------------------
3040
2880 -------- ?? unknown
3041
2884 -------- ?? unknown
3042
--------------------------------------------------------------------------------
3043
2888
3044
bit 0
3045
Decoder + osd ?? unknown
3046
0 = Normal
3047
1 = Misaligned fields (Correctable through 289C & 28A4)
3049
bit 4
3050
?? unknown
3052
bit 8
3053
?? unknown
3055
Warning: Bad values will require a firmware reload to recover.
3056
Known to be bad are 0x000,0x011,0x100,0x111
3057
--------------------------------------------------------------------------------
3058
288C
3059
bits 0:15
3060
osd ?? unknown
3061
Appears to affect the osd position stability. The higher the value the
3062
more unstable it becomes. Decoder output remains stable.
3064
bits 16:31
3065
osd ?? unknown
3066
Same as bits 0:15
3068
--------------------------------------------------------------------------------
3069
2890
3070
bits 0:11
3071
Decoder output horizontal offset.
3073
Horizontal offset moves the video image right. A small left shift is
3074
possible, but it's better to use reg 2870 for that due to its greater
3075
range.
3077
NOTE: Video corruption will occur if video window is shifted off the right
3078
edge. To avoid this read the notes for 2834 & 2838.
3079
--------------------------------------------------------------------------------
3080
2894
3081
bits 0:23
3082
Decoder output video surround colour.
3084
Contains the colour (in yuv) used to fill the screen when the video is
3085
running in a window.
3086
--------------------------------------------------------------------------------
3087
2898
3088
bits 0:23
3089
Decoder video window colour
3090
Contains the colour (in yuv) used to fill the video window when the
3091
video is turned off.
3093
bit 24
3094
Decoder video output
3095
0 = Video on
3096
1 = Video off
3098
bit 28
3099
Decoder plane order
3100
0 = Y,UV
3101
1 = UV,Y
3103
bit 29
3104
Decoder second plane byte order
3105
0 = Normal (UV)
3106
1 = Swapped (VU)
3108
In normal usage, the first plane is Y & the second plane is UV. Though the
3109
order of the planes can be swapped, only the byte order of the second plane
3110
can be swapped. This isn't much use for the Y plane, but can be useful for
3111
the UV plane.
3113
--------------------------------------------------------------------------------
3114
289C
3115
bits 0:15
3116
Decoder vertical field offset 1
3118
bits 16:31
3119
Decoder vertical field offset 2
3121
Controls field output vertical alignment. The higher the number, the lower
3122
the image on screen. Known starting values are 0x011E0017 (NTSC) &
3123
0x01500017 (PAL)
3124
--------------------------------------------------------------------------------
3125
28A0
3126
bits 0:15
3127
Decoder & osd width in pixels
3129
bits 16:31
3130
Decoder & osd height in pixels
3132
All output from the decoder & osd are disabled beyond this area. Decoder
3133
output will simply go black outside of this region. If the osd tries to
3134
exceed this area it will become corrupt.
3135
--------------------------------------------------------------------------------
3136
28A4
3137
bits 0:11
3138
osd left shift.
3140
Has a range of 0x770->0x7FF. With the exception of 0, any value outside of
3141
this range corrupts the osd.
3142
--------------------------------------------------------------------------------
3143
28A8
3144
bits 0:15
3145
osd vertical field offset 1
3147
bits 16:31
3148
osd vertical field offset 2
3150
Controls field output vertical alignment. The higher the number, the lower
3151
the image on screen. Known starting values are 0x011E0017 (NTSC) &
3152
0x01500017 (PAL)
3153
--------------------------------------------------------------------------------
3154
28AC -------- ?? unknown
3155
|
3156
V
3157
28BC -------- ?? unknown
3158
--------------------------------------------------------------------------------
3159
28C0
3160
bit 0
3161
Current output field
3162
0 = first field
3163
1 = second field
3165
bits 16:31
3166
Current scanline
3167
The scanline counts from the top line of the first field
3168
through to the last line of the second field.
3169
--------------------------------------------------------------------------------
3170
28C4 -------- ?? unknown
3171
|
3172
V
3173
28F8 -------- ?? unknown
3174
--------------------------------------------------------------------------------
3175
28FC
3176
bit 0
3177
?? unknown
3178
0 = Normal
3179
1 = Breaks decoder & osd output
3180
--------------------------------------------------------------------------------
3181
2900
3182
bits 0:31
3183
Decoder vertical Y alias register 1
3184
---------------
3185
2904
3186
bits 0:31
3187
Decoder vertical Y alias register 2
3188
---------------
3189
2908
3190
bits 0:31
3191
Decoder vertical Y alias trigger
3193
These three registers control the vertical aliasing filter for the Y plane.
3194
Operation is similar to the horizontal Y filter (2804). The only real
3195
difference is that there are only two registers to set before accessing
3196
the trigger register (2908). As for the horizontal filter, the values are
3197
taken from a lookup table in the firmware, and the procedure must be
3198
repeated 16 times to fully program the filter.
3199
--------------------------------------------------------------------------------
3200
290C
3201
bits 0:31
3202
Decoder vertical UV alias register 1
3203
---------------
3204
2910
3205
bits 0:31
3206
Decoder vertical UV alias register 2
3207
---------------
3208
2914
3209
bits 0:31
3210
Decoder vertical UV alias trigger
3212
These three registers control the vertical aliasing filter for the UV
3213
plane. Operation is the same as the Y filter, with 2914 being the trigger.
3214
--------------------------------------------------------------------------------
3215
2918
3216
bits 0:15
3217
Decoder Y source height in pixels
3219
bits 16:31
3220
Decoder Y destination height in pixels
3221
---------------
3222
291C
3223
bits 0:15
3224
Decoder UV source height in pixels divided by 2
3226
bits 16:31
3227
Decoder UV destination height in pixels
3229
NOTE: For both registers, the resulting image must be fully visible on
3230
screen. If the image exceeds the bottom edge both the source and
3231
destination size must be adjusted to reflect the visible portion. For the
3232
source height, you must take into account the scaling when calculating the
3233
new value.
3234
--------------------------------------------------------------------------------
3235
2920
3236
bits 0:31
3237
Decoder Y vertical scaling
3238
Normally = Reg 2930 >> 2
3239
---------------
3240
2924
3241
bits 0:31
3242
Decoder Y vertical scaling
3243
Normally = Reg 2920 + 0x514
3244
---------------
3245
2928
3246
bits 0:31
3247
Decoder UV vertical scaling
3248
When enlarging = Reg 2930 >> 2
3249
When reducing = Reg 2930 >> 3
3250
---------------
3251
292C
3252
bits 0:31
3253
Decoder UV vertical scaling
3254
Normally = Reg 2928 + 0x514
3255
---------------
3256
2930
3257
bits 0:31
3258
Decoder 'master' value for vertical scaling
3259
---------------
3260
2934
3261
bits 0:31
3262
Decoder ?? unknown - Y vertical scaling
3263
---------------
3264
2938
3265
bits 0:31
3266
Decoder Y vertical scaling
3267
Normally = Reg 2930
3268
---------------
3269
293C
3270
bits 0:31
3271
Decoder ?? unknown - Y vertical scaling
3272
---------------
3273
2940
3274
bits 0:31
3275
Decoder UV vertical scaling
3276
When enlarging = Reg 2930 >> 1
3277
When reducing = Reg 2930
3278
---------------
3279
2944
3280
bits 0:31
3281
Decoder ?? unknown - UV vertical scaling
3282
---------------
3283
2948
3284
bits 0:31
3285
Decoder UV vertical scaling
3286
Normally = Reg 2940
3287
---------------
3288
294C
3289
bits 0:31
3290
Decoder ?? unknown - UV vertical scaling
3292
Most of these registers either control vertical scaling, or appear linked
3293
to it in some way. Register 2930 contains the 'master' value & all other
3294
registers can be calculated from that one. You must also remember to
3295
correctly set the divider in Reg 296C
3297
To enlarge:
3298
Reg 2930 = (source_height * 0x00200000) / destination_height
3299
Reg 296C = No divide
3301
To reduce from full size down to half size:
3302
Reg 2930 = (source_height/2 * 0x00200000) / destination height
3303
Reg 296C = Divide by 2
3305
To reduce from half down to quarter.
3306
Reg 2930 = (source_height/4 * 0x00200000) / destination height
3307
Reg 296C = Divide by 4
3309
--------------------------------------------------------------------------------
3310
2950
3311
bits 0:15
3312
Decoder Y line index into display buffer, first field
3314
bits 16:31
3315
Decoder Y vertical line skip, first field
3316
--------------------------------------------------------------------------------
3317
2954
3318
bits 0:15
3319
Decoder Y line index into display buffer, second field
3321
bits 16:31
3322
Decoder Y vertical line skip, second field
3323
--------------------------------------------------------------------------------
3324
2958
3325
bits 0:15
3326
Decoder UV line index into display buffer, first field
3328
bits 16:31
3329
Decoder UV vertical line skip, first field
3330
--------------------------------------------------------------------------------
3331
295C
3332
bits 0:15
3333
Decoder UV line index into display buffer, second field
3335
bits 16:31
3336
Decoder UV vertical line skip, second field
3337
--------------------------------------------------------------------------------
3338
2960
3339
bits 0:15
3340
Decoder destination height minus 1
3342
bits 16:31
3343
Decoder destination height divided by 2
3344
--------------------------------------------------------------------------------
3345
2964
3346
bits 0:15
3347
Decoder Y vertical offset, second field
3349
bits 16:31
3350
Decoder Y vertical offset, first field
3352
These two registers shift the Y plane up. The higher the number, the
3353
greater the shift.
3354
--------------------------------------------------------------------------------
3355
2968
3356
bits 0:15
3357
Decoder UV vertical offset, second field
3359
bits 16:31
3360
Decoder UV vertical offset, first field
3362
These two registers shift the UV plane up. The higher the number, the
3363
greater the shift.
3364
--------------------------------------------------------------------------------
3365
296C
3366
bits 0:1
3367
Decoder vertical Y output size divider
3368
00 = No divide
3369
01 = Divide by 2
3370
10 = Divide by 4
3372
bits 8:9
3373
Decoder vertical UV output size divider
3374
00 = No divide
3375
01 = Divide by 2
3376
10 = Divide by 4
3377
--------------------------------------------------------------------------------
3378
2970
3379
bit 0
3380
Decoder ?? unknown
3381
0 = Normal
3382
1 = Affect video output levels
3384
bit 16
3385
Decoder ?? unknown
3386
0 = Normal
3387
1 = Disable vertical filter
3389
--------------------------------------------------------------------------------
3390
2974 -------- ?? unknown
3391
|
3392
V
3393
29EF -------- ?? unknown
3394
--------------------------------------------------------------------------------
3395
2A00
3396
bits 0:2
3397
osd colour mode
3398
000 = 8 bit indexed
3399
001 = 16 bit (565)
3400
010 = 15 bit (555)
3401
011 = 12 bit (444)
3402
100 = 32 bit (8888)
3404
bits 4:5
3405
osd display bpp
3406
01 = 8 bit
3407
10 = 16 bit
3408
11 = 32 bit
3410
bit 8
3411
osd global alpha
3412
0 = Off
3413
1 = On
3415
bit 9
3416
osd local alpha
3417
0 = Off
3418
1 = On
3420
bit 10
3421
osd colour key
3422
0 = Off
3423
1 = On
3425
bit 11
3426
osd ?? unknown
3427
Must be 1
3429
bit 13
3430
osd colour space
3431
0 = ARGB
3432
1 = AYVU
3434
bits 16:31
3435
osd ?? unknown
3436
Must be 0x001B (some kind of buffer pointer ?)
3438
When the bits-per-pixel is set to 8, the colour mode is ignored and
3439
assumed to be 8 bit indexed. For 16 & 32 bits-per-pixel the colour depth
3440
is honoured, and when using a colour depth that requires fewer bytes than
3441
allocated the extra bytes are used as padding. So for a 32 bpp with 8 bit
3442
index colour, there are 3 padding bytes per pixel. It's also possible to
3443
select 16bpp with a 32 bit colour mode. This results in the pixel width
3444
being doubled, but the color key will not work as expected in this mode.
3446
Colour key is as it suggests. You designate a colour which will become
3447
completely transparent. When using 565, 555 or 444 colour modes, the
3448
colour key is always 16 bits wide. The colour to key on is set in Reg 2A18.
3450
Local alpha works differently depending on the colour mode. For 32bpp & 8
3451
bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being
3452
transparent and 255 being solid. For the 16bpp modes 555 & 444, the unused
3453
bit(s) act as a simple transparency switch, with 0 being solid & 1 being
3454
fully transparent. There is no local alpha support for 16bit 565.
3456
Global alpha is a 256 step transparency that applies to the entire osd,
3457
with 0 being transparent & 255 being solid.
3459
It's possible to combine colour key, local alpha & global alpha.
3460
--------------------------------------------------------------------------------
3461
2A04
3462
bits 0:15
3463
osd x coord for left edge
3465
bits 16:31
3466
osd y coord for top edge
3467
---------------
3468
2A08
3469
bits 0:15
3470
osd x coord for right edge
3472
bits 16:31
3473
osd y coord for bottom edge
3475
For both registers, (0,0) = top left corner of the display area. These
3476
registers do not control the osd size, only where it's positioned & how
3477
much is visible. The visible osd area cannot exceed the right edge of the
3478
display, otherwise the osd will become corrupt. See reg 2A10 for
3479
setting osd width.
3480
--------------------------------------------------------------------------------
3481
2A0C
3482
bits 0:31
3483
osd buffer index
3485
An index into the osd buffer. Slowly incrementing this moves the osd left,
3486
wrapping around onto the right edge
3487
--------------------------------------------------------------------------------
3488
2A10
3489
bits 0:11
3490
osd buffer 32 bit word width
3492
Contains the width of the osd measured in 32 bit words. This means that all
3493
colour modes are restricted to a byte width which is divisible by 4.
3494
--------------------------------------------------------------------------------
3495
2A14
3496
bits 0:15
3497
osd height in pixels
3499
bits 16:32
3500
osd line index into buffer
3501
osd will start displaying from this line.
3502
--------------------------------------------------------------------------------
3503
2A18
3504
bits 0:31
3505
osd colour key
3507
Contains the colour value which will be transparent.
3508
--------------------------------------------------------------------------------
3509
2A1C
3510
bits 0:7
3511
osd global alpha
3513
Contains the global alpha value (equiv ivtvfbctl --alpha XX)
3514
--------------------------------------------------------------------------------
3515
2A20 -------- ?? unknown
3516
|
3517
V
3518
2A2C -------- ?? unknown
3519
--------------------------------------------------------------------------------
3520
2A30
3521
bits 0:7
3522
osd colour to change in indexed palette
3523
---------------
3524
2A34
3525
bits 0:31
3526
osd colour for indexed palette
3528
To set the new palette, first load the index of the colour to change into
3529
2A30, then load the new colour into 2A34. The full palette is 256 colours,
3530
so the index range is 0x00-0xFF
3531
--------------------------------------------------------------------------------
3532
2A38 -------- ?? unknown
3533
2A3C -------- ?? unknown
3534
--------------------------------------------------------------------------------
3535
2A40
3536
bits 0:31
3537
osd ?? unknown
3539
Affects overall brightness, wrapping around to black
3540
--------------------------------------------------------------------------------
3541
2A44
3542
bits 0:31
3543
osd ?? unknown
3545
Green tint
3546
--------------------------------------------------------------------------------
3547
2A48
3548
bits 0:31
3549
osd ?? unknown
3551
Red tint
3552
--------------------------------------------------------------------------------
3553
2A4C
3554
bits 0:31
3555
osd ?? unknown
3557
Affects overall brightness, wrapping around to black
3558
--------------------------------------------------------------------------------
3559
2A50
3560
bits 0:31
3561
osd ?? unknown
3563
Colour shift
3564
--------------------------------------------------------------------------------
3565
2A54
3566
bits 0:31
3567
osd ?? unknown
3569
Colour shift
3570
--------------------------------------------------------------------------------
3571
2A58 -------- ?? unknown
3572
|
3573
V
3574
2AFC -------- ?? unknown
3575
--------------------------------------------------------------------------------
3576
2B00
3577
bit 0
3578
osd filter control
3579
0 = filter off
3580
1 = filter on
3582
bits 1:4
3583
osd ?? unknown
3585
--------------------------------------------------------------------------------
3587
The cx231xx DMA engine
3588
----------------------
3591
This page describes the structures and procedures used by the cx2341x DMA
3592
engine.
3594
Introduction
3595
~~~~~~~~~~~~
3597
The cx2341x PCI interface is busmaster capable. This means it has a DMA
3598
engine to efficiently transfer large volumes of data between the card and main
3599
memory without requiring help from a CPU. Like most hardware, it must operate
3600
on contiguous physical memory. This is difficult to come by in large quantities
3601
on virtual memory machines.
3603
Therefore, it also supports a technique called "scatter-gather". The card can
3604
transfer multiple buffers in one operation. Instead of allocating one large
3605
contiguous buffer, the driver can allocate several smaller buffers.
3607
In practice, I've seen the average transfer to be roughly 80K, but transfers
3608
above 128K were not uncommon, particularly at startup. The 128K figure is
3609
important, because that is the largest block that the kernel can normally
3610
allocate. Even still, 128K blocks are hard to come by, so the driver writer is
3611
urged to choose a smaller block size and learn the scatter-gather technique.
3613
Mailbox #10 is reserved for DMA transfer information.
3615
Note: the hardware expects little-endian data ('intel format').
3617
Flow
3618
~~~~
3620
This section describes, in general, the order of events when handling DMA
3621
transfers. Detailed information follows this section.
3623
- The card raises the Encoder interrupt.
3624
- The driver reads the transfer type, offset and size from Mailbox #10.
3625
- The driver constructs the scatter-gather array from enough free dma buffers
3626
to cover the size.
3627
- The driver schedules the DMA transfer via the ScheduleDMAtoHost API call.
3628
- The card raises the DMA Complete interrupt.
3629
- The driver checks the DMA status register for any errors.
3630
- The driver post-processes the newly transferred buffers.
3632
NOTE! It is possible that the Encoder and DMA Complete interrupts get raised
3633
simultaneously. (End of the last, start of the next, etc.)
3635
Mailbox #10
3636
~~~~~~~~~~~
3638
The Flags, Command, Return Value and Timeout fields are ignored.
3640
- Name: Mailbox #10
3641
- Results[0]: Type: 0: MPEG.
3642
- Results[1]: Offset: The position relative to the card's memory space.
3643
- Results[2]: Size: The exact number of bytes to transfer.
3645
My speculation is that since the StartCapture API has a capture type of "RAW"
3646
available, that the type field will have other values that correspond to YUV
3647
and PCM data.
3649
Scatter-Gather Array
3650
~~~~~~~~~~~~~~~~~~~~
3652
The scatter-gather array is a contiguously allocated block of memory that
3653
tells the card the source and destination of each data-block to transfer.
3654
Card "addresses" are derived from the offset supplied by Mailbox #10. Host
3655
addresses are the physical memory location of the target DMA buffer.
3657
Each S-G array element is a struct of three 32-bit words. The first word is
3658
the source address, the second is the destination address. Both take up the
3659
entire 32 bits. The lowest 18 bits of the third word is the transfer byte
3660
count. The high-bit of the third word is the "last" flag. The last-flag tells
3661
the card to raise the DMA_DONE interrupt. From hard personal experience, if
3662
you forget to set this bit, the card will still "work" but the stream will
3663
most likely get corrupted.
3665
The transfer count must be a multiple of 256. Therefore, the driver will need
3666
to track how much data in the target buffer is valid and deal with it
3667
accordingly.
3669
Array Element:
3671
- 32-bit Source Address
3672
- 32-bit Destination Address
3673
- 14-bit reserved (high bit is the last flag)
3674
- 18-bit byte count
3676
DMA Transfer Status
3677
~~~~~~~~~~~~~~~~~~~
3679
Register 0x0004 holds the DMA Transfer Status:
3681
- bit 0: read completed
3682
- bit 1: write completed
3683
- bit 2: DMA read error
3684
- bit 3: DMA write error
3685
- bit 4: Scatter-Gather array error
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
메모리 맵과 제어 레지스터
1-156cx2341x의 32비트 long word는 little-endian입니다. 이 문서는 공개 명세가 아니라 `ivtvctl -O min=...,max=...` 같은 메모리 덤프와 실험으로 역공학한 결과이므로, 레지스터 이름과 의미에는 누락이나 오류가 있을 수 있습니다.
BAR0에는 64 MiB가 노출됩니다. encoder 메모리는 `0x00000000`, decoder 메모리는 `0x01000000`, register 영역은 `0x02000000`에서 시작합니다. 각 레지스터는 32비트이며 DMA, encoder/decoder 제어, SDRAM, display, audio, VPU/SPU/APU 제어 영역으로 나뉩니다.
범위의미
0x00000000-0x00ffffffencoder 메모리
0x01000000-0x01ffffffdecoder 메모리
0x02000000-0x020000ffDMA 레지스터
0x02000400-0x020004ffVPU 레지스터
0x02000500-0x020005ffAPU 레지스터
0x02000600-0x020006ffhardware block 레지스터
0x02000800-0x020008ffdecoder 레지스터
0x02002800-0x02002b00PVR350 video decoder/OSD 레지스터
주소와 symbol은 원문 표기를 유지했습니다.
비트의미
31capture 시작
30end-of-stream
29VBI capture
28reset event
27encoder DMA 완료
24decoder audio mode 변경
22decoder data request
20decoder DMA 완료
19VBI reinsert
18DMA 오류
아직 문서화되지 않은 항목은 encoder/decoder API의 추가 명령과 decoder `VTRACE`입니다. 이 목록은 확인된 사실과 추정치를 구분해 읽어야 합니다.
.. SPDX-License-Identifier: GPL-2.0
The cx2341x driver
==================
Memory at cx2341x chips
-----------------------
This section describes the cx2341x memory map and documents some of the
register space.
.. note:: the memory long words are little-endian ('intel format').
.. warning::
This information was figured out from searching through the memory
and registers, this information may not be correct and is certainly
not complete, and was not derived from anything more than searching
through the memory space with commands like:
.. code-block:: none
ivtvctl -O min=0x02000000,max=0x020000ff
So take this as is, I'm always searching for more stuff, it's a large
register space :-).
Memory Map
~~~~~~~~~~
The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
(Base Address Register 0). The addresses here are offsets relative to the
address held in BAR0.
.. code-block:: none
0x00000000-0x00ffffff Encoder memory space
0x00000000-0x0003ffff Encode.rom
???-??? MPEG buffer(s)
???-??? Raw video capture buffer(s)
???-??? Raw audio capture buffer(s)
???-??? Display buffers (6 or 9)
0x01000000-0x01ffffff Decoder memory space
0x01000000-0x0103ffff Decode.rom
???-??? MPEG buffers(s)
0x0114b000-0x0115afff Audio.rom (deprecated?)
0x02000000-0x0200ffff Register Space
Registers
~~~~~~~~~
The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
All of these registers are 32 bits wide.
.. code-block:: none
DMA Registers 0x000-0xff:
0x00 - Control:
0=reset/cancel, 1=read, 2=write, 4=stop
0x04 - DMA status:
1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error
0x08 - pci DMA pointer for read link list
0x0c - pci DMA pointer for write link list
0x10 - read/write DMA enable:
1=read enable, 2=write enable
0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes
0x18 - ??
0x1c - always 0x20 or 32, smaller values slow down DMA transactions
0x20 - always value of 0x780a010a
0x24-0x3c - usually just random values???
0x40 - Interrupt status
0x44 - Write a bit here and shows up in Interrupt status 0x40
0x48 - Interrupt Mask
0x4C - always value of 0xfffdffff,
if changed to 0xffffffff DMA write interrupts break.
0x50 - always 0xffffffff
0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are
3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the
interrupt masks???).
0x60-0x7C - random values
0x80 - first write linked list reg, for Encoder Memory addr
0x84 - first write linked list reg, for pci memory addr
0x88 - first write linked list reg, for length of buffer in memory addr
(|0x80000000 or this for last link)
0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
from linked list addr in reg 0x0c, firmware must push through or
something.
0xe0 - first (and only) read linked list reg, for pci memory addr
0xe4 - first (and only) read linked list reg, for Decoder memory addr
0xe8 - first (and only) read linked list reg, for length of buffer
0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
Memory locations for Encoder Buffers 0x700-0x7ff:
These registers show offsets of memory locations pertaining to each
buffer area used for encoding, have to shift them by <<1 first.
- 0x07F8: Encoder SDRAM refresh
- 0x07FC: Encoder SDRAM pre-charge
Memory locations for Decoder Buffers 0x800-0x8ff:
These registers show offsets of memory locations pertaining to each
buffer area used for decoding, have to shift them by <<1 first.
- 0x08F8: Decoder SDRAM refresh
- 0x08FC: Decoder SDRAM pre-charge
Other memory locations:
- 0x2800: Video Display Module control
- 0x2D00: AO (audio output?) control
- 0x2D24: Bytes Flushed
- 0x7000: LSB I2C write clock bit (inverted)
- 0x7004: LSB I2C write data bit (inverted)
- 0x7008: LSB I2C read clock bit
- 0x700c: LSB I2C read data bit
- 0x9008: GPIO get input state
- 0x900c: GPIO set output state
- 0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)
- 0x9050: SPU control
- 0x9054: Reset HW blocks
- 0x9058: VPU control
- 0xA018: Bit6: interrupt pending?
- 0xA064: APU command
Interrupt Status Register
~~~~~~~~~~~~~~~~~~~~~~~~~
The definition of the bits in the interrupt status register 0x0040, and the
interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to
execute.
- bit 31 Encoder Start Capture
- bit 30 Encoder EOS
- bit 29 Encoder VBI capture
- bit 28 Encoder Video Input Module reset event
- bit 27 Encoder DMA complete
- bit 24 Decoder audio mode change detection event (through event notification)
- bit 22 Decoder data request
- bit 20 Decoder DMA complete
- bit 19 Decoder VBI re-insertion
- bit 18 Decoder DMA err (linked-list bad)
Missing documentation
---------------------
- Encoder API post(?)
- Decoder API post(?)
- Decoder VTRACE event
firmware 탐색과 업로드
157-209encoder와 decoder firmware image는 각각 정확히 256 KiB입니다. encoder image의 첫 두 word는 `0x0000da7`, `0xaa55bb66`, decoder image는 `0x00003a7`, `0xaa55bb66`이어야 합니다. 이 signature와 크기로 올바른 image를 식별합니다.
단계작업
1encoder와 decoder를 정지하고 decoder VSYNC를 끔
2VPU/SPU를 멈추고 firmware 실행을 halt
3hardware block, display, audio와 VPU/SPU/APU를 reset
4SDRAM precharge/refresh를 초기화하고 안정화 시간을 기다림
5encoder image를 0x00000000, decoder image를 0x01000000에 전송
6SPU와 VPU를 다시 활성화하고 status register로 시작 여부 확인
원문의 register write 값과 sleep 순서는 장치 초기화 계약입니다. 특히 reset 해제와 SDRAM 초기화 순서를 임의로 바꾸면 firmware가 시작되지 않을 수 있으므로 아래 영어 원문의 각 write를 그대로 따라야 합니다.
The cx2341x firmware upload
---------------------------
This document describes how to upload the cx2341x firmware to the card.
How to find
~~~~~~~~~~~
See the web pages of the various projects that uses this chip for information
on how to obtain the firmware.
The firmware stored in a Windows driver can be detected as follows:
- Each firmware image is 256k bytes.
- The 1st 32-bit word of the Encoder image is 0x0000da7
- The 1st 32-bit word of the Decoder image is 0x00003a7
- The 2nd 32-bit word of both images is 0xaa55bb66
How to load
~~~~~~~~~~~
- Issue the FWapi command to stop the encoder if it is running. Wait for the
command to complete.
- Issue the FWapi command to stop the decoder if it is running. Wait for the
command to complete.
- Issue the I2C command to the digitizer to stop emitting VSYNC events.
- Issue the FWapi command to halt the encoder's firmware.
- Sleep for 10ms.
- Issue the FWapi command to halt the decoder's firmware.
- Sleep for 10ms.
- Write 0x00000000 to register 0x2800 to stop the Video Display Module.
- Write 0x00000005 to register 0x2D00 to stop the AO (audio output?).
- Write 0x00000000 to register 0xA064 to ping? the APU.
- Write 0xFFFFFFFE to register 0x9058 to stop the VPU.
- Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.
- Write 0x00000001 to register 0x9050 to stop the SPU.
- Sleep for 10ms.
- Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
- Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
- Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
- Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
- Sleep for 512ms. (600ms is recommended)
- Transfer the encoder's firmware image to offset 0 in Encoder memory space.
- Transfer the decoder's firmware image to offset 0 in Decoder memory space.
- Use a read-modify-write operation to Clear bit 0 of register 0x9050 to
re-enable the SPU.
- Sleep for 1 second.
- Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058
to re-enable the VPU.
- Sleep for 1 second.
- Issue status API commands to both firmware images to verify.
firmware mailbox와 API 호출 규약
210-284firmware API는 고정 크기 mailbox 배열을 사용합니다. 16바이트 signature는 256바이트 경계에 있고, 뒤에는 각각 20개의 32비트 word로 구성된 mailbox 20개가 옵니다. 앞의 10개는 API 호출, 뒤의 10개는 event notification용입니다.
word필드의미
0Flagsbit 2=firmware 처리 완료, bit 1=입력 준비, bit 0=mailbox 사용 중
1Commandfirmware API command enum
2Return`0` 성공, `-1` 정의되지 않은 command
3Timeouttimeout 값
4-19Param/Result호출 전 parameter 16개, 완료 후 result 16개
호출자는 비어 있는 mailbox를 점유한 뒤 command와 parameter를 쓰고 `I` 비트를 세웁니다. firmware가 처리하면 `O` 비트를 세우며, 호출자는 return/result를 읽고 mailbox를 해제합니다. event mailbox는 같은 형식을 쓰지만 Flags·Command·Return·Timeout은 무시하고 16개 result만 전달합니다.
How to call the firmware API
----------------------------
The preferred calling convention is known as the firmware mailbox. The
mailboxes are basically a fixed length array that serves as the call-stack.
Firmware mailboxes can be located by searching the encoder and decoder memory
for a 16 byte signature. That signature will be located on a 256-byte boundary.
Signature:
.. code-block:: none
0x78, 0x56, 0x34, 0x12, 0x12, 0x78, 0x56, 0x34,
0x34, 0x12, 0x78, 0x56, 0x56, 0x34, 0x12, 0x78
The firmware implements 20 mailboxes of 20 32-bit words. The first 10 are
reserved for API calls. The second 10 are used by the firmware for event
notification.
====== =================
Index Name
====== =================
0 Flags
1 Command
2 Return value
3 Timeout
4-19 Parameter/Result
====== =================
The flags are defined in the following table. The direction is from the
perspective of the firmware.
==== ========== ============================================
Bit Direction Purpose
==== ========== ============================================
2 O Firmware has processed the command.
1 I Driver has finished setting the parameters.
0 I Driver is using this mailbox.
==== ========== ============================================
The command is a 32-bit enumerator. The API specifics may be found in this
chapter.
The return value is a 32-bit enumerator. Only two values are currently defined:
- 0=success
- -1=command undefined.
There are 16 parameters/results 32-bit fields. The driver populates these fields
with values for all the parameters required by the call. The driver overwrites
these fields with result values returned by the call.
The timeout value protects the card from a hung driver thread. If the driver
doesn't handle the completed call within the timeout specified, the firmware
will reset that mailbox.
To make an API call, the driver iterates over each mailbox looking for the
first one available (bit 0 has been cleared). The driver sets that bit, fills
in the command enumerator, the timeout value and any required parameters. The
driver then sets the parameter ready bit (bit 1). The firmware scans the
mailboxes for pending commands, processes them, sets the result code, populates
the result value array with that call's return values and sets the call
complete bit (bit 2). Once bit 2 is set, the driver should retrieve the results
and clear all the flags. If the driver does not perform this task within the
time set in the timeout register, the firmware will reset that mailbox.
Event notifications are sent from the firmware to the host. The host tells the
firmware which events it is interested in via an API call. That call tells the
firmware which notification mailbox to use. The firmware signals the host via
an interrupt. Only the 16 Results fields are used, the Flags, Command, Return
value and Timeout words are not used.
OSD framebuffer, pixel format와 상태 조회
285-428OSD API는 decoder firmware에 속하므로 `cx23415`에서만 사용할 수 있습니다. `GET_FRAMEBUFFER`는 OSD buffer의 base address와 길이를 반환하고, pixel format API는 indexed/RGB/ARGB 형식을 조회하거나 설정합니다.
CommandEnumParameter 또는 Result
CX2341X_OSD_GET_FRAMEBUFFER65/0x41Result[0]=base address, Result[1]=length
CX2341X_OSD_GET_PIXEL_FORMAT66/0x42Result[0]: 0=indexed8, 1=RGB565, 2=ARGB1555, 3=ARGB1444, 4=ARGB8888
CX2341X_OSD_SET_PIXEL_FORMAT67/0x43Param[0]=동일 pixel format enum
CX2341X_OSD_GET_STATE68/0x44Result[0]: bit0 on/off, bits1:2 alpha control, bits3:5 pixel format
CX2341X_OSD_SET_STATE69/0x45Param[0]: 0=off, 1=on
CX2341X_OSD_GET_OSD_COORDS70/0x46buffer address, stride, line 수, horizontal/vertical offset 반환
OSD coordinate의 stride 단위는 pixel이며 address는 decoder address space를 기준으로 합니다. state bitfield와 pixel format enum은 서로 연동되므로 format 변경 뒤 state를 다시 확인하는 편이 안전합니다.
OSD firmware API description
----------------------------
.. note:: this API is part of the decoder firmware, so it's cx23415 only.
CX2341X_OSD_GET_FRAMEBUFFER
~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 65/0x41
Description
^^^^^^^^^^^
Return base and length of contiguous OSD memory.
Result[0]
^^^^^^^^^
OSD base address
Result[1]
^^^^^^^^^
OSD length
CX2341X_OSD_GET_PIXEL_FORMAT
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 66/0x42
Description
^^^^^^^^^^^
Query OSD format
Result[0]
^^^^^^^^^
0=8bit index
1=16bit RGB 5:6:5
2=16bit ARGB 1:5:5:5
3=16bit ARGB 1:4:4:4
4=32bit ARGB 8:8:8:8
CX2341X_OSD_SET_PIXEL_FORMAT
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 67/0x43
Description
^^^^^^^^^^^
Assign pixel format
Param[0]
^^^^^^^^
- 0=8bit index
- 1=16bit RGB 5:6:5
- 2=16bit ARGB 1:5:5:5
- 3=16bit ARGB 1:4:4:4
- 4=32bit ARGB 8:8:8:8
CX2341X_OSD_GET_STATE
~~~~~~~~~~~~~~~~~~~~~
Enum: 68/0x44
Description
^^^^^^^^^^^
Query OSD state
Result[0]
^^^^^^^^^
- Bit 0 0=off, 1=on
- Bits 1:2 alpha control
- Bits 3:5 pixel format
CX2341X_OSD_SET_STATE
~~~~~~~~~~~~~~~~~~~~~
Enum: 69/0x45
Description
^^^^^^^^^^^
OSD switch
Param[0]
^^^^^^^^
0=off, 1=on
CX2341X_OSD_GET_OSD_COORDS
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 70/0x46
Description
^^^^^^^^^^^
Retrieve coordinates of OSD area blended with video
Result[0]
^^^^^^^^^
OSD buffer address
Result[1]
^^^^^^^^^
Stride in pixels
Result[2]
^^^^^^^^^
Lines in OSD buffer
Result[3]
^^^^^^^^^
Horizontal offset in buffer
Result[4]
^^^^^^^^^
Vertical offset in buffer
OSD와 screen 좌표, global alpha
429-578CommandEnumParameter 또는 Result
CX2341X_OSD_SET_OSD_COORDS71/0x47buffer address, pixel stride, line 수, horizontal/vertical offset
CX2341X_OSD_GET_SCREEN_COORDS72/0x48top-left와 bottom-right의 horizontal/vertical 좌표
CX2341X_OSD_SET_SCREEN_COORDS73/0x49top-left와 원문상 bottom-left의 horizontal/vertical 좌표
CX2341X_OSD_GET_GLOBAL_ALPHA74/0x4AResult[0]=global alpha on/off, Result[1]=8-bit alpha
CX2341X_OSD_SET_GLOBAL_ALPHA75/0x4BParam[0]=global on/off, Param[1]=8-bit alpha, Param[2]=local alpha(0=on, 1=off)
screen coordinate는 표시 가능한 사각형을 정하고 OSD coordinate는 decoder buffer 안에서 읽을 위치와 stride를 정합니다. `SET_SCREEN_COORDS`의 마지막 두 parameter를 원문은 bottom left로 표현하므로, 구현에서 bottom-right로 추정해 바꾸지 말고 firmware 동작으로 확인해야 합니다.
global alpha는 화면 전체에 적용되는 8비트 투명도입니다. local alpha의 on/off 값은 일반적인 boolean과 반대로 `0=on`, `1=off`이므로 그대로 전달해야 합니다.
CX2341X_OSD_SET_OSD_COORDS
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 71/0x47
Description
^^^^^^^^^^^
Assign the coordinates of the OSD area to blend with video
Param[0]
^^^^^^^^
buffer address
Param[1]
^^^^^^^^
buffer stride in pixels
Param[2]
^^^^^^^^
lines in buffer
Param[3]
^^^^^^^^
horizontal offset
Param[4]
^^^^^^^^
vertical offset
CX2341X_OSD_GET_SCREEN_COORDS
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 72/0x48
Description
^^^^^^^^^^^
Retrieve OSD screen area coordinates
Result[0]
^^^^^^^^^
top left horizontal offset
Result[1]
^^^^^^^^^
top left vertical offset
Result[2]
^^^^^^^^^
bottom right horizontal offset
Result[3]
^^^^^^^^^
bottom right vertical offset
CX2341X_OSD_SET_SCREEN_COORDS
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 73/0x49
Description
^^^^^^^^^^^
Assign the coordinates of the screen area to blend with video
Param[0]
^^^^^^^^
top left horizontal offset
Param[1]
^^^^^^^^
top left vertical offset
Param[2]
^^^^^^^^
bottom left horizontal offset
Param[3]
^^^^^^^^
bottom left vertical offset
CX2341X_OSD_GET_GLOBAL_ALPHA
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 74/0x4A
Description
^^^^^^^^^^^
Retrieve OSD global alpha
Result[0]
^^^^^^^^^
global alpha: 0=off, 1=on
Result[1]
^^^^^^^^^
bits 0:7 global alpha
CX2341X_OSD_SET_GLOBAL_ALPHA
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 75/0x4B
Description
^^^^^^^^^^^
Update global alpha
Param[0]
^^^^^^^^
global alpha: 0=off, 1=on
Param[1]
^^^^^^^^
global alpha (8 bits)
Param[2]
^^^^^^^^
local alpha: 0=on, 1=off
OSD blend, flicker와 BLT copy
579-747`SET_BLEND_COORDS`는 display buffer 안의 horizontal/vertical offset을 정합니다. 원문은 이 command를 `Enum: 78/0x4C`로 적는데, 78과 0x4C의 수치가 일치하지 않습니다. 이 불일치는 교정하지 않고 원문 그대로 보존합니다.
CommandEnum핵심 필드
CX2341X_OSD_SET_BLEND_COORDS78/0x4CParam[0]=horizontal, Param[1]=vertical offset
CX2341X_OSD_GET_FLICKER_STATE79/0x4FResult[0]: 0=off, 1=on
CX2341X_OSD_SET_FLICKER_STATE80/0x50Param[0]: 0=off, 1=on
CX2341X_OSD_BLT_COPY82/0x52ROP, alpha source, blend formula, width/height, mask, destination/source address와 stride
`BLT_COPY`의 Param[0]은 source와 destination boolean 조합을 선택하는 4비트 ROP truth table입니다. Param[1]은 alpha를 source, destination 또는 composite에서 가져올지 정하고, Param[2]는 네 가지 blending formula 중 하나를 선택합니다.
Param[3:4]는 width/height, Param[5]는 destination pixel mask, Param[6:7]은 destination rectangle address와 dword stride, Param[8:9]는 source stride와 source rectangle address입니다. 각 bit 조합의 정확한 수식은 아래 원문 표를 보존합니다.
CX2341X_OSD_SET_BLEND_COORDS
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 78/0x4C
Description
^^^^^^^^^^^
Move start of blending area within display buffer
Param[0]
^^^^^^^^
horizontal offset in buffer
Param[1]
^^^^^^^^
vertical offset in buffer
CX2341X_OSD_GET_FLICKER_STATE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 79/0x4F
Description
^^^^^^^^^^^
Retrieve flicker reduction module state
Result[0]
^^^^^^^^^
flicker state: 0=off, 1=on
CX2341X_OSD_SET_FLICKER_STATE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 80/0x50
Description
^^^^^^^^^^^
Set flicker reduction module state
Param[0]
^^^^^^^^
State: 0=off, 1=on
CX2341X_OSD_BLT_COPY
~~~~~~~~~~~~~~~~~~~~
Enum: 82/0x52
Description
^^^^^^^^^^^
BLT copy
Param[0]
^^^^^^^^
.. code-block:: none
'0000' zero
'0001' ~destination AND ~source
'0010' ~destination AND source
'0011' ~destination
'0100' destination AND ~source
'0101' ~source
'0110' destination XOR source
'0111' ~destination OR ~source
'1000' ~destination AND ~source
'1001' destination XNOR source
'1010' source
'1011' ~destination OR source
'1100' destination
'1101' destination OR ~source
'1110' destination OR source
'1111' one
Param[1]
^^^^^^^^
Resulting alpha blending
- '01' source_alpha
- '10' destination_alpha
- '11' source_alpha*destination_alpha+1
(zero if both source and destination alpha are zero)
Param[2]
^^^^^^^^
.. code-block:: none
'00' output_pixel = source_pixel
'01' if source_alpha=0:
output_pixel = destination_pixel
if 256 > source_alpha > 1:
output_pixel = ((source_alpha + 1)*source_pixel +
(255 - source_alpha)*destination_pixel)/256
'10' if destination_alpha=0:
output_pixel = source_pixel
if 255 > destination_alpha > 0:
output_pixel = ((255 - destination_alpha)*source_pixel +
(destination_alpha + 1)*destination_pixel)/256
'11' if source_alpha=0:
source_temp = 0
if source_alpha=255:
source_temp = source_pixel*256
if 255 > source_alpha > 0:
source_temp = source_pixel*(source_alpha + 1)
if destination_alpha=0:
destination_temp = 0
if destination_alpha=255:
destination_temp = destination_pixel*256
if 255 > destination_alpha > 0:
destination_temp = destination_pixel*(destination_alpha + 1)
output_pixel = (source_temp + destination_temp)/256
Param[3]
^^^^^^^^
width
Param[4]
^^^^^^^^
height
Param[5]
^^^^^^^^
destination pixel mask
Param[6]
^^^^^^^^
destination rectangle start address
Param[7]
^^^^^^^^
destination stride in dwords
Param[8]
^^^^^^^^
source stride in dwords
Param[9]
^^^^^^^^
source rectangle start address
OSD fill, text, window와 chroma key
748-959CommandEnum핵심 필드
CX2341X_OSD_BLT_FILL83/0x530x52의 ROP/alpha/blend + width, height, mask, destination, stride, fill color
CX2341X_OSD_BLT_TEXT84/0x548-bit alpha text source + destination/source stride와 address, fill color
CX2341X_OSD_SET_FRAMEBUFFER_WINDOW86/0x56width, height, top-left horizontal/vertical; screen 안에 완전히 들어와야 함
CX2341X_OSD_SET_CHROMA_KEY96/0x60Param[0]=state, Param[1]=transparent color
CX2341X_OSD_GET_ALPHA_CONTENT_INDEX97/0x61Result[0]=0..15
CX2341X_OSD_SET_ALPHA_CONTENT_INDEX98/0x62Param[0]=0..15
`BLT_FILL`과 `BLT_TEXT`의 첫 세 parameter는 `BLT_COPY(0x52)`와 동일합니다. text source는 pixel당 8비트 alpha를 제공하며 fill color와 조합됩니다. framebuffer window가 screen 경계를 벗어나면 출력이 손상될 수 있습니다.
chroma key는 지정한 색을 완전히 투명하게 만들고 alpha content index는 16개 entry 중 하나를 선택합니다. 색의 실제 표현은 현재 OSD pixel format에 맞춰야 합니다.
CX2341X_OSD_BLT_FILL
~~~~~~~~~~~~~~~~~~~~
Enum: 83/0x53
Description
^^^^^^^^^^^
BLT fill color
Param[0]
^^^^^^^^
Same as Param[0] on API 0x52
Param[1]
^^^^^^^^
Same as Param[1] on API 0x52
Param[2]
^^^^^^^^
Same as Param[2] on API 0x52
Param[3]
^^^^^^^^
width
Param[4]
^^^^^^^^
height
Param[5]
^^^^^^^^
destination pixel mask
Param[6]
^^^^^^^^
destination rectangle start address
Param[7]
^^^^^^^^
destination stride in dwords
Param[8]
^^^^^^^^
color fill value
CX2341X_OSD_BLT_TEXT
~~~~~~~~~~~~~~~~~~~~
Enum: 84/0x54
Description
^^^^^^^^^^^
BLT for 8 bit alpha text source
Param[0]
^^^^^^^^
Same as Param[0] on API 0x52
Param[1]
^^^^^^^^
Same as Param[1] on API 0x52
Param[2]
^^^^^^^^
Same as Param[2] on API 0x52
Param[3]
^^^^^^^^
width
Param[4]
^^^^^^^^
height
Param[5]
^^^^^^^^
destination pixel mask
Param[6]
^^^^^^^^
destination rectangle start address
Param[7]
^^^^^^^^
destination stride in dwords
Param[8]
^^^^^^^^
source stride in dwords
Param[9]
^^^^^^^^
source rectangle start address
Param[10]
^^^^^^^^^
color fill value
CX2341X_OSD_SET_FRAMEBUFFER_WINDOW
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 86/0x56
Description
^^^^^^^^^^^
Positions the main output window on the screen. The coordinates must be
such that the entire window fits on the screen.
Param[0]
^^^^^^^^
window width
Param[1]
^^^^^^^^
window height
Param[2]
^^^^^^^^
top left window corner horizontal offset
Param[3]
^^^^^^^^
top left window corner vertical offset
CX2341X_OSD_SET_CHROMA_KEY
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 96/0x60
Description
^^^^^^^^^^^
Chroma key switch and color
Param[0]
^^^^^^^^
state: 0=off, 1=on
Param[1]
^^^^^^^^
color
CX2341X_OSD_GET_ALPHA_CONTENT_INDEX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 97/0x61
Description
^^^^^^^^^^^
Retrieve alpha content index
Result[0]
^^^^^^^^^
alpha content index, Range 0:15
CX2341X_OSD_SET_ALPHA_CONTENT_INDEX
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 98/0x62
Description
^^^^^^^^^^^
Assign alpha content index
Param[0]
^^^^^^^^
alpha content index, range 0:15
Encoder ping, capture와 기본 stream 설정
960-1132CommandEnum의미와 필드
CX2341X_ENC_PING_FW128/0x80동작 없음; firmware 응답 확인
CX2341X_ENC_START_CAPTURE129/0x81stream type 0=MPEG, 1=Raw, 2=Raw passthrough, 3=VBI; Raw subtype bit0 YUV, bit1 PCM, bit2 VBI, bit3 decoder, bit4 host
CX2341X_ENC_STOP_CAPTURE130/0x82Param[0] 0=GOP 끝에서 정지/IRQ, 1=즉시 정지; stream type과 subtype 지정
CX2341X_ENC_SET_AUDIO_ID137/0x89audio transport stream ID
CX2341X_ENC_SET_VIDEO_ID139/0x8Bvideo transport stream ID
CX2341X_ENC_SET_PCR_ID141/0x8DPCR packet stream ID
CX2341X_ENC_SET_FRAME_RATE143/0x8F0=30 fps, 1=25 fps; 다음 GOP에서 적용
CX2341X_ENC_SET_FRAME_SIZE145/0x91height line 수(기본 480), width pixel 수(기본 720)
capture를 시작하기 전에 모든 encoding parameter를 초기화해야 합니다. stream type이 Raw일 때만 subtype bitmask가 의미를 가지며, capture는 명시된 frame 수에 도달하거나 stop command를 받을 때까지 계속됩니다.
Encoder firmware API description
--------------------------------
CX2341X_ENC_PING_FW
~~~~~~~~~~~~~~~~~~~
Enum: 128/0x80
Description
^^^^^^^^^^^
Does nothing. Can be used to check if the firmware is responding.
CX2341X_ENC_START_CAPTURE
~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 129/0x81
Description
^^^^^^^^^^^
Commences the capture of video, audio and/or VBI data. All encoding
parameters must be initialized prior to this API call. Captures frames
continuously or until a predefined number of frames have been captured.
Param[0]
^^^^^^^^
Capture stream type:
- 0=MPEG
- 1=Raw
- 2=Raw passthrough
- 3=VBI
Param[1]
^^^^^^^^
Bitmask:
- Bit 0 when set, captures YUV
- Bit 1 when set, captures PCM audio
- Bit 2 when set, captures VBI (same as param[0]=3)
- Bit 3 when set, the capture destination is the decoder
(same as param[0]=2)
- Bit 4 when set, the capture destination is the host
.. note:: this parameter is only meaningful for RAW capture type.
CX2341X_ENC_STOP_CAPTURE
~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 130/0x82
Description
^^^^^^^^^^^
Ends a capture in progress
Param[0]
^^^^^^^^
- 0=stop at end of GOP (generates IRQ)
- 1=stop immediate (no IRQ)
Param[1]
^^^^^^^^
Stream type to stop, see param[0] of API 0x81
Param[2]
^^^^^^^^
Subtype, see param[1] of API 0x81
CX2341X_ENC_SET_AUDIO_ID
~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 137/0x89
Description
^^^^^^^^^^^
Assigns the transport stream ID of the encoded audio stream
Param[0]
^^^^^^^^
Audio Stream ID
CX2341X_ENC_SET_VIDEO_ID
~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 139/0x8B
Description
^^^^^^^^^^^
Set video transport stream ID
Param[0]
^^^^^^^^
Video stream ID
CX2341X_ENC_SET_PCR_ID
~~~~~~~~~~~~~~~~~~~~~~
Enum: 141/0x8D
Description
^^^^^^^^^^^
Assigns the transport stream ID for PCR packets
Param[0]
^^^^^^^^
PCR Stream ID
CX2341X_ENC_SET_FRAME_RATE
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 143/0x8F
Description
^^^^^^^^^^^
Set video frames per second. Change occurs at start of new GOP.
Param[0]
^^^^^^^^
- 0=30fps
- 1=25fps
CX2341X_ENC_SET_FRAME_SIZE
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 145/0x91
Description
^^^^^^^^^^^
Select video stream encoding resolution.
Param[0]
^^^^^^^^
Height in lines. Default 480
Param[1]
^^^^^^^^
Width in pixels. Default 720
Encoder bitrate, GOP와 aspect ratio
1133-1230CommandEnumParameter
CX2341X_ENC_SET_BIT_RATE149/0x95CBR/VBR, 평균 bitrate, peak/400, mux/400, VBR padding, VBV buffer
CX2341X_ENC_SET_GOP_PROPERTIES151/0x97GOP 크기(최대 34), I/P 사이 B frame 수+1
CX2341X_ENC_SET_ASPECT_RATIO153/0x990001=1:1, 0010=4:3, 0011=16:9, 0100=2.21:1
bitrate의 Param[2]와 Param[3]은 초당 bit 수를 400으로 나눈 값입니다. 원문 관찰상 Param[3:4]는 보통 0이고 Param[5]는 사용되지 않는 듯하지만, 이는 확정된 hardware 명세가 아니라 관찰 결과입니다.
GOP 크기는 `(B-frame 수 + 1)`의 배수여야 합니다. 예를 들어 `IBBPBBPBBPBB`는 GOP 크기 12, 두 B frame에 1을 더한 parameter 값 3을 사용합니다. aspect ratio 변경은 다음 GOP 시작에서 적용됩니다.
CX2341X_ENC_SET_BIT_RATE
~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 149/0x95
Description
^^^^^^^^^^^
Assign average video stream bitrate.
Param[0]
^^^^^^^^
0=variable bitrate, 1=constant bitrate
Param[1]
^^^^^^^^
bitrate in bits per second
Param[2]
^^^^^^^^
peak bitrate in bits per second, divided by 400
Param[3]
^^^^^^^^
Mux bitrate in bits per second, divided by 400. May be 0 (default).
Param[4]
^^^^^^^^
Rate Control VBR Padding
Param[5]
^^^^^^^^
VBV Buffer used by encoder
.. note::
#) Param\[3\] and Param\[4\] seem to be always 0
#) Param\[5\] doesn't seem to be used.
CX2341X_ENC_SET_GOP_PROPERTIES
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 151/0x97
Description
^^^^^^^^^^^
Setup the GOP structure
Param[0]
^^^^^^^^
GOP size (maximum is 34)
Param[1]
^^^^^^^^
Number of B frames between the I and P frame, plus 1.
For example: IBBPBBPBBPBB --> GOP size: 12, number of B frames: 2+1 = 3
.. note::
GOP size must be a multiple of (B-frames + 1).
CX2341X_ENC_SET_ASPECT_RATIO
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 153/0x99
Description
^^^^^^^^^^^
Sets the encoding aspect ratio. Changes in the aspect ratio take effect
at the start of the next GOP.
Param[0]
^^^^^^^^
- '0000' forbidden
- '0001' 1:1 square
- '0010' 4:3
- '0011' 16:9
- '0100' 2.21:1
- '0101' to '1111' reserved
CX2341X_ENC_SET_DNR_FILTER_MODEEncoder noise reduction와 spatial filter
1231-1348CommandEnumParameter
CX2341X_ENC_SET_DNR_FILTER_MODE155/0x9Bbit0 spatial auto/manual, bit1 temporal auto/manual; median 0=off, 1=horizontal, 2=vertical, 3=H/V, 4=diagonal
CX2341X_ENC_SET_DNR_FILTER_PROPS157/0x9Dmanual spatial 0..15, manual temporal 0..31
CX2341X_ENC_SET_CORING_LEVELS159/0x9Fluminance/chrominance median filter의 upper/lower threshold, 각각 0..255
CX2341X_ENC_SET_SPATIAL_FILTER_TYPE161/0xA1luma off/1D H/1D V/2D separable/2D non-separable, chroma off/1D H
manual filter 값은 해당 filter가 `SET_DNR_FILTER_MODE`에서 manual로 설정됐을 때만 의미가 있습니다. coring은 luminance와 chrominance 각각에 대해 median filter가 활성화되는 상한·하한 threshold를 지정합니다.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 155/0x9B
Description
^^^^^^^^^^^
Assign Dynamic Noise Reduction operating mode
Param[0]
^^^^^^^^
Bit0: Spatial filter, set=auto, clear=manual
Bit1: Temporal filter, set=auto, clear=manual
Param[1]
^^^^^^^^
Median filter:
- 0=Disabled
- 1=Horizontal
- 2=Vertical
- 3=Horiz/Vert
- 4=Diagonal
CX2341X_ENC_SET_DNR_FILTER_PROPS
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 157/0x9D
Description
^^^^^^^^^^^
These Dynamic Noise Reduction filter values are only meaningful when
the respective filter is set to "manual" (See API 0x9B)
Param[0]
^^^^^^^^
Spatial filter: default 0, range 0:15
Param[1]
^^^^^^^^
Temporal filter: default 0, range 0:31
CX2341X_ENC_SET_CORING_LEVELS
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 159/0x9F
Description
^^^^^^^^^^^
Assign Dynamic Noise Reduction median filter properties.
Param[0]
^^^^^^^^
Threshold above which the luminance median filter is enabled.
Default: 0, range 0:255
Param[1]
^^^^^^^^
Threshold below which the luminance median filter is enabled.
Default: 255, range 0:255
Param[2]
^^^^^^^^
Threshold above which the chrominance median filter is enabled.
Default: 0, range 0:255
Param[3]
^^^^^^^^
Threshold below which the chrominance median filter is enabled.
Default: 255, range 0:255
CX2341X_ENC_SET_SPATIAL_FILTER_TYPE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 161/0xA1
Description
^^^^^^^^^^^
Assign spatial prefilter parameters
Param[0]
^^^^^^^^
Luminance filter
- 0=Off
- 1=1D Horizontal
- 2=1D Vertical
- 3=2D H/V Separable (default)
- 4=2D Symmetric non-separable
Param[1]
^^^^^^^^
Chrominance filter
- 0=Off
- 1=1D Horizontal (default)
Encoder VBI line, stream type와 output port
1349-1451CommandEnumParameter
CX2341X_ENC_SET_VBI_LINE183/0xB7bits0:4 line, bit31 field; all bits=all lines, feature enable, slicing, luma/chroma samples
CX2341X_ENC_SET_STREAM_TYPE185/0xB9Program/Transport/MPEG1/PES/DVD/VCD/SVCD/DVD_S1/DVD_S2 stream
CX2341X_ENC_SET_OUTPUT_PORT187/0xBB0=Memory(DMA), 1=Streaming, 2=Serial; Param[1]은 0 권장
VBI slicing과 sample count는 거의 구현되지 않은 것으로 보이므로 원문은 0을 권합니다. 최근 firmware의 Transport stream은 동작하지 않고, 오래된 firmware에서도 timestamp가 신뢰하기 어렵다는 주의가 있습니다.
output port 0은 PCI DMA로 host memory에 복사할 때, 1은 pvrusb 또는 cx88-blackbird처럼 다른 chip으로 stream할 때 사용합니다. 두 번째 parameter는 알려지지 않았고 0 이외의 값은 동작을 깨뜨리는 것으로 관찰됐습니다.
CX2341X_ENC_SET_VBI_LINE
~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 183/0xB7
Description
^^^^^^^^^^^
Selects VBI line number.
Param[0]
^^^^^^^^
- Bits 0:4 line number
- Bit 31 0=top_field, 1=bottom_field
- Bits 0:31 all set specifies "all lines"
Param[1]
^^^^^^^^
VBI line information features: 0=disabled, 1=enabled
Param[2]
^^^^^^^^
Slicing: 0=None, 1=Closed Caption
Almost certainly not implemented. Set to 0.
Param[3]
^^^^^^^^
Luminance samples in this line.
Almost certainly not implemented. Set to 0.
Param[4]
^^^^^^^^
Chrominance samples in this line
Almost certainly not implemented. Set to 0.
CX2341X_ENC_SET_STREAM_TYPE
~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 185/0xB9
Description
^^^^^^^^^^^
Assign stream type
.. note::
Transport stream is not working in recent firmwares.
And in older firmwares the timestamps in the TS seem to be
unreliable.
Param[0]
^^^^^^^^
- 0=Program stream
- 1=Transport stream
- 2=MPEG1 stream
- 3=PES A/V stream
- 5=PES Video stream
- 7=PES Audio stream
- 10=DVD stream
- 11=VCD stream
- 12=SVCD stream
- 13=DVD_S1 stream
- 14=DVD_S2 stream
CX2341X_ENC_SET_OUTPUT_PORT
~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 187/0xBB
Description
^^^^^^^^^^^
Assign stream output port. Normally 0 when the data is copied through
the PCI bus (DMA), and 1 when the data is streamed to another chip
(pvrusb and cx88-blackbird).
Param[0]
^^^^^^^^
- 0=Memory (default)
- 1=Streaming
- 2=Serial
Param[1]
^^^^^^^^
Unknown, but leaving this to 0 seems to work best. Indications are that
this might have to do with USB support, although passing anything but 0
only breaks things.
Encoder MPEG audio 속성
1452-1552`CX2341X_ENC_SET_AUDIO_PROPERTIES`(189/0xBD)는 encoding 중에도 호출할 수 있습니다. Param[0] 하나에 sample rate, MPEG layer, bitrate index, channel mode, joint-stereo extension, emphasis, CRC, copyright, generation을 packing합니다.
비트의미
0:100=44.1 kHz, 01=48 kHz, 10=32 kHz, 11=reserved
2:301=Layer I, 10=Layer II; ISO11172 표기와 불일치 가능
4:7Layer별 bitrate index; 전체 대응표는 아래 원문 유지
8:9Stereo, JointStereo, Dual, Mono
10:11joint stereo intensity subband 경계
12:13None, 50/15 us, reserved, CCITT J.17 emphasis
14CRC off/on
15copyright off/on
16copy/original
시험 결과 Layer II만 실제로 동작하며 최소 bitrate는 192 kbps여야 한다고 기록되어 있습니다. `cx23415`는 Joint Stereo를 올바르게 decode하지 못합니다. Layer II에서는 bitrate와 mode의 모든 조합이 허용되지 않으므로 ISO11172-3 Annex B 표도 확인해야 합니다.
CX2341X_ENC_SET_AUDIO_PROPERTIES
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 189/0xBD
Description
^^^^^^^^^^^
Set audio stream properties, may be called while encoding is in progress.
.. note::
All bitfields are consistent with ISO11172 documentation except
bits 2:3 which ISO docs define as:
- '11' Layer I
- '10' Layer II
- '01' Layer III
- '00' Undefined
This discrepancy may indicate a possible error in the documentation.
Testing indicated that only Layer II is actually working, and that
the minimum bitrate should be 192 kbps.
Param[0]
^^^^^^^^
Bitmask:
.. code-block:: none
0:1 '00' 44.1Khz
'01' 48Khz
'10' 32Khz
'11' reserved
2:3 '01'=Layer I
'10'=Layer II
4:7 Bitrate:
Index | Layer I | Layer II
------+-------------+------------
'0000' | free format | free format
'0001' | 32 kbit/s | 32 kbit/s
'0010' | 64 kbit/s | 48 kbit/s
'0011' | 96 kbit/s | 56 kbit/s
'0100' | 128 kbit/s | 64 kbit/s
'0101' | 160 kbit/s | 80 kbit/s
'0110' | 192 kbit/s | 96 kbit/s
'0111' | 224 kbit/s | 112 kbit/s
'1000' | 256 kbit/s | 128 kbit/s
'1001' | 288 kbit/s | 160 kbit/s
'1010' | 320 kbit/s | 192 kbit/s
'1011' | 352 kbit/s | 224 kbit/s
'1100' | 384 kbit/s | 256 kbit/s
'1101' | 416 kbit/s | 320 kbit/s
'1110' | 448 kbit/s | 384 kbit/s
.. note::
For Layer II, not all combinations of total bitrate
and mode are allowed. See ISO11172-3 3-Annex B,
Table 3-B.2
8:9 '00'=Stereo
'01'=JointStereo
'10'=Dual
'11'=Mono
.. note::
The cx23415 cannot decode Joint Stereo properly.
10:11 Mode Extension used in joint_stereo mode.
In Layer I and II they indicate which subbands are in
intensity_stereo. All other subbands are coded in stereo.
'00' subbands 4-31 in intensity_stereo, bound==4
'01' subbands 8-31 in intensity_stereo, bound==8
'10' subbands 12-31 in intensity_stereo, bound==12
'11' subbands 16-31 in intensity_stereo, bound==16
12:13 Emphasis:
'00' None
'01' 50/15uS
'10' reserved
'11' CCITT J.17
14 CRC:
'0' off
'1' on
15 Copyright:
'0' off
'1' on
16 Generation:
'0' copy
'1' original
Encoder halt, version, sequence와 program index
1553-1689CommandEnum의미
CX2341X_ENC_HALT_FW195/0xC3firmware 중지; 다시 upload할 때까지 API 처리 안 함
CX2341X_ENC_GET_VERSION196/0xC4bits0:15 build, 16:23 minor, 24:31 major
CX2341X_ENC_SET_GOP_CLOSURE197/0xC50=open, 1=closed GOP
CX2341X_ENC_GET_SEQ_END198/0xC6Result[0]=마지막 buffer 여부, Result[1]=마지막 buffer 크기
CX2341X_ENC_SET_PGM_INDEX_INFO199/0xC7I/P/B frame index ring buffer를 encoder memory에 할당
program index entry는 frame length, 64비트 file offset, picture type mask, 33비트 PTS를 저장합니다. 최대 400개 entry의 ring buffer이며 `table_ptr`은 새 entry를 쓸 encoder memory 주소이고 끝에서 wrap합니다.
picture mask는 0=off, 1=I, 3=I/P, 7=I/P/B지만 실제 관찰상 항상 I/P/B를 index합니다. Result[0]은 table 시작 offset, Result[1]은 요청 수 이하로 실제 할당된 entry 수입니다.
CX2341X_ENC_HALT_FW
~~~~~~~~~~~~~~~~~~~
Enum: 195/0xC3
Description
^^^^^^^^^^^
The firmware is halted and no further API calls are serviced until the
firmware is uploaded again.
CX2341X_ENC_GET_VERSION
~~~~~~~~~~~~~~~~~~~~~~~
Enum: 196/0xC4
Description
^^^^^^^^^^^
Returns the version of the encoder firmware.
Result[0]
^^^^^^^^^
Version bitmask:
- Bits 0:15 build
- Bits 16:23 minor
- Bits 24:31 major
CX2341X_ENC_SET_GOP_CLOSURE
~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 197/0xC5
Description
^^^^^^^^^^^
Assigns the GOP open/close property.
Param[0]
^^^^^^^^
- 0=Open
- 1=Closed
CX2341X_ENC_GET_SEQ_END
~~~~~~~~~~~~~~~~~~~~~~~
Enum: 198/0xC6
Description
^^^^^^^^^^^
Obtains the sequence end code of the encoder's buffer. When a capture
is started a number of interrupts are still generated, the last of
which will have Result[0] set to 1 and Result[1] will contain the size
of the buffer.
Result[0]
^^^^^^^^^
State of the transfer (1 if last buffer)
Result[1]
^^^^^^^^^
If Result[0] is 1, this contains the size of the last buffer, undefined
otherwise.
CX2341X_ENC_SET_PGM_INDEX_INFO
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 199/0xC7
Description
^^^^^^^^^^^
Sets the Program Index Information.
The information is stored as follows:
.. code-block:: c
struct info {
u32 length; // Length of this frame
u32 offset_low; // Offset in the file of the
u32 offset_high; // start of this frame
u32 mask1; // Bits 0-2 are the type mask:
// 1=I, 2=P, 4=B
// 0=End of Program Index, other fields
// are invalid.
u32 pts; // The PTS of the frame
u32 mask2; // Bit 0 is bit 32 of the pts.
};
u32 table_ptr;
struct info index[400];
The table_ptr is the encoder memory address in the table were
*new* entries will be written.
.. note:: This is a ringbuffer, so the table_ptr will wraparound.
Param[0]
^^^^^^^^
Picture Mask:
- 0=No index capture
- 1=I frames
- 3=I,P frames
- 7=I,P,B frames
(Seems to be ignored, it always indexes I, P and B frames)
Param[1]
^^^^^^^^
Elements requested (up to 400)
Result[0]
^^^^^^^^^
Offset in the encoder memory of the start of the table.
Result[1]
^^^^^^^^^
Number of allocated elements up to a maximum of Param[1]
Encoder VBI 구성과 DMA mailbox 10
1690-1812CommandEnumParameter 또는 Result
CX2341X_ENC_SET_VBI_CONFIG200/0xC8sliced/raw, insertion mode, stream ID, interrupt당 frame, 총 frame, start/stop code, lines/frame, bytes/line
CX2341X_ENC_SET_DMA_BLOCK_SIZE201/0xC9크기와 단위(0=bytes, 1=frames); byte 단위는 2^7, 2^8, 2^9
CX2341X_ENC_GET_PREV_DMA_INFO_MB_10202/0xCAResult: stream type, address offset, 최대 transfer size; interrupt bit27과 mailbox 10 사용
VBI config의 mode bit는 `0=sliced`, `1=raw`입니다. insertion bits는 extension/user data, private packet, 별도 stream 조합을 고르고 bits8:15는 보통 stream ID `0xBD`를 사용합니다.
raw mode result는 실제 interrupt당 frame 수, 실제 frame 수와 raw VBI data 시작 memory offset을 반환합니다. 원문의 `Rage`와 `start or raw`는 각각 오타로 보이지만 의미를 임의 수정하지 않고 원문 블록에 보존합니다.
CX2341X_ENC_SET_VBI_CONFIG
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 200/0xC8
Description
^^^^^^^^^^^
Configure VBI settings
Param[0]
^^^^^^^^
Bitmap:
.. code-block:: none
0 Mode '0' Sliced, '1' Raw
1:3 Insertion:
'000' insert in extension & user data
'001' insert in private packets
'010' separate stream and user data
'111' separate stream and private data
8:15 Stream ID (normally 0xBD)
Param[1]
^^^^^^^^
Frames per interrupt (max 8). Only valid in raw mode.
Param[2]
^^^^^^^^
Total raw VBI frames. Only valid in raw mode.
Param[3]
^^^^^^^^
Start codes
Param[4]
^^^^^^^^
Stop codes
Param[5]
^^^^^^^^
Lines per frame
Param[6]
^^^^^^^^
Byte per line
Result[0]
^^^^^^^^^
Observed frames per interrupt in raw mode only. Rage 1 to Param[1]
Result[1]
^^^^^^^^^
Observed number of frames in raw mode. Range 1 to Param[2]
Result[2]
^^^^^^^^^
Memory offset to start or raw VBI data
CX2341X_ENC_SET_DMA_BLOCK_SIZE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 201/0xC9
Description
^^^^^^^^^^^
Set DMA transfer block size
Param[0]
^^^^^^^^
DMA transfer block size in bytes or frames. When unit is bytes,
supported block sizes are 2^7, 2^8 and 2^9 bytes.
Param[1]
^^^^^^^^
Unit: 0=bytes, 1=frames
CX2341X_ENC_GET_PREV_DMA_INFO_MB_10
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 202/0xCA
Description
^^^^^^^^^^^
Returns information on the previous DMA transfer in conjunction with
bit 27 of the interrupt mask. Uses mailbox 10.
Result[0]
^^^^^^^^^
Type of stream
Result[1]
^^^^^^^^^
Address Offset
Result[2]
^^^^^^^^^
Maximum size of transfer
Encoder DMA 상태와 입력 제어
1813-1936CommandEnum의미
CX2341X_ENC_GET_PREV_DMA_INFO_MB_9203/0xCBread/write 완료, DMA read/write 오류, S-G 오류, DMA type와 33비트 PTS
CX2341X_ENC_SCHED_DMA_TO_HOST204/0xCClinked list memory address, list length(단위 미상), DMA type(0=MPEG)
CX2341X_ENC_INITIALIZE_INPUT205/0xCDvideo input 초기화
CX2341X_ENC_SET_FRAME_DROP_RATE208/0xD0capture frame마다 건너뛸 frame 수
CX2341X_ENC_PAUSE_ENCODER210/0xD20=pause, 1=continue; pause 중 frame drop
CX2341X_ENC_REFRESH_INPUT211/0xD3video input refresh
mailbox 9 status의 bit0/1은 read/write 완료, bit2/3은 DMA read/write 오류, bit4는 scatter-gather array 오류입니다. PTS는 Result[2]의 하위 32비트와 Result[3]의 bit32로 구성됩니다.
CX2341X_ENC_GET_PREV_DMA_INFO_MB_9
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 203/0xCB
Description
^^^^^^^^^^^
Returns information on the previous DMA transfer in conjunction with
bit 27 or 18 of the interrupt mask. Uses mailbox 9.
Result[0]
^^^^^^^^^
Status bits:
- 0 read completed
- 1 write completed
- 2 DMA read error
- 3 DMA write error
- 4 Scatter-Gather array error
Result[1]
^^^^^^^^^
DMA type
Result[2]
^^^^^^^^^
Presentation Time Stamp bits 0..31
Result[3]
^^^^^^^^^
Presentation Time Stamp bit 32
CX2341X_ENC_SCHED_DMA_TO_HOST
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 204/0xCC
Description
^^^^^^^^^^^
Setup DMA to host operation
Param[0]
^^^^^^^^
Memory address of link list
Param[1]
^^^^^^^^
Length of link list (wtf: what units ???)
Param[2]
^^^^^^^^
DMA type (0=MPEG)
CX2341X_ENC_INITIALIZE_INPUT
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 205/0xCD
Description
^^^^^^^^^^^
Initializes the video input
CX2341X_ENC_SET_FRAME_DROP_RATE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 208/0xD0
Description
^^^^^^^^^^^
For each frame captured, skip specified number of frames.
Param[0]
^^^^^^^^
Number of frames to skip
CX2341X_ENC_PAUSE_ENCODER
~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 210/0xD2
Description
^^^^^^^^^^^
During a pause condition, all frames are dropped instead of being encoded.
Param[0]
^^^^^^^^
- 0=Pause encoding
- 1=Continue encoding
CX2341X_ENC_REFRESH_INPUT
~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 211/0xD3
Description
^^^^^^^^^^^
Refreshes the video input
Encoder copyright, event, VSYNC와 placeholder
1937-2091CommandEnumParameter
CX2341X_ENC_SET_COPYRIGHT212/0xD40=copyright 없음, 1=copyright 있음
CX2341X_ENC_SET_EVENT_NOTIFICATION213/0xD5event, notification enable, interrupt bit, mailbox slot(-1=없음)
CX2341X_ENC_SET_NUM_VSYNC_LINES214/0xD6field 1/2 line 수; SAA7114/7115/Micronas별 값
CX2341X_ENC_SET_PLACEHOLDER215/0xD7custom MPEG user data 위치, 삽입 주기, DWORD 수와 data 0..8
event 0은 encoder input refresh이며 host가 해당 interrupt bit를 unmask해야 notification을 받습니다. VSYNC line 수는 analog decoder에 따라 SAA7114 `0x00EF/0x00EF`, SAA7115 `0x00F0/0x00F0`, Micronas `0x0105/0x0106`을 사용합니다.
placeholder는 extension/user data 또는 stream ID `0xBD` private packet에 최대 9 DWORD의 custom data를 넣습니다. 삽입 주기는 private packet이면 frame, extension/user data이면 GOP 단위입니다.
CX2341X_ENC_SET_COPYRIGHT
~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 212/0xD4
Description
^^^^^^^^^^^
Sets stream copyright property
Param[0]
^^^^^^^^
- 0=Stream is not copyrighted
- 1=Stream is copyrighted
CX2341X_ENC_SET_EVENT_NOTIFICATION
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 213/0xD5
Description
^^^^^^^^^^^
Setup firmware to notify the host about a particular event. Host must
unmask the interrupt bit.
Param[0]
^^^^^^^^
Event (0=refresh encoder input)
Param[1]
^^^^^^^^
Notification 0=disabled 1=enabled
Param[2]
^^^^^^^^
Interrupt bit
Param[3]
^^^^^^^^
Mailbox slot, -1 if no mailbox required.
CX2341X_ENC_SET_NUM_VSYNC_LINES
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 214/0xD6
Description
^^^^^^^^^^^
Depending on the analog video decoder used, this assigns the number
of lines for field 1 and 2.
Param[0]
^^^^^^^^
Field 1 number of lines:
- 0x00EF for SAA7114
- 0x00F0 for SAA7115
- 0x0105 for Micronas
Param[1]
^^^^^^^^
Field 2 number of lines:
- 0x00EF for SAA7114
- 0x00F0 for SAA7115
- 0x0106 for Micronas
CX2341X_ENC_SET_PLACEHOLDER
~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 215/0xD7
Description
^^^^^^^^^^^
Provides a mechanism of inserting custom user data in the MPEG stream.
Param[0]
^^^^^^^^
- 0=extension & user data
- 1=private packet with stream ID 0xBD
Param[1]
^^^^^^^^
Rate at which to insert data, in units of frames (for private packet)
or GOPs (for ext. & user data)
Param[2]
^^^^^^^^
Number of data DWORDs (below) to insert
Param[3]
^^^^^^^^
Custom data 0
Param[4]
^^^^^^^^
Custom data 1
Param[5]
^^^^^^^^
Custom data 2
Param[6]
^^^^^^^^
Custom data 3
Param[7]
^^^^^^^^
Custom data 4
Param[8]
^^^^^^^^
Custom data 5
Param[9]
^^^^^^^^
Custom data 6
Param[10]
^^^^^^^^^
Custom data 7
Param[11]
^^^^^^^^^
Custom data 8
Encoder mute, crop와 miscellaneous ioctl
2092-2200CommandEnumParameter
CX2341X_ENC_MUTE_VIDEO217/0xD9bit0 mute; bits8:15 V, 16:23 U, 24:31 Y로 대체 frame 색 지정
CX2341X_ENC_MUTE_AUDIO218/0xDA0=unmute, 1=mute; silent MPEG audio stream 생성
CX2341X_ENC_SET_VERT_CROP_LINE219/0xDBSAA7114 + raw VBI + 60 Hz이면 10001, 그 외 0
CX2341X_ENC_MISC220/0xDCParam[0]=command 번호, Param[1]=값인 ioctl형 확장 명령
`ENC_MISC` command 1..14는 초기 SCR, quality mode, VIM protection, DVD PTS, USB flush, quantization matrix, DVD navigation packet, scene detection, VIM history/field order, audio interface reset, volume delay와 audio delay를 제어합니다.
command 7은 2048바이트의 `0xbf` private stream 2 packet을 약 4 frame마다 삽입하며 payload는 application이 채워야 합니다. command 12는 argument 없이 audio interface를 reset하고 cx2584x에서 필요합니다.
CX2341X_ENC_MUTE_VIDEO
~~~~~~~~~~~~~~~~~~~~~~
Enum: 217/0xD9
Description
^^^^^^^^^^^
Video muting
Param[0]
^^^^^^^^
Bit usage:
.. code-block:: none
0 '0'=video not muted
'1'=video muted, creates frames with the YUV color defined below
1:7 Unused
8:15 V chrominance information
16:23 U chrominance information
24:31 Y luminance information
CX2341X_ENC_MUTE_AUDIO
~~~~~~~~~~~~~~~~~~~~~~
Enum: 218/0xDA
Description
^^^^^^^^^^^
Audio muting
Param[0]
^^^^^^^^
- 0=audio not muted
- 1=audio muted (produces silent mpeg audio stream)
CX2341X_ENC_SET_VERT_CROP_LINE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 219/0xDB
Description
^^^^^^^^^^^
Something to do with 'Vertical Crop Line'
Param[0]
^^^^^^^^
If saa7114 and raw VBI capture and 60 Hz, then set to 10001.
Else 0.
CX2341X_ENC_MISC
~~~~~~~~~~~~~~~~
Enum: 220/0xDC
Description
^^^^^^^^^^^
Miscellaneous actions. Not known for 100% what it does. It's really a
sort of ioctl call. The first parameter is a command number, the second
the value.
Param[0]
^^^^^^^^
Command number:
.. code-block:: none
1=set initial SCR value when starting encoding (works).
2=set quality mode (apparently some test setting).
3=setup advanced VIM protection handling.
Always 1 for the cx23416 and 0 for cx23415.
4=generate DVD compatible PTS timestamps
5=USB flush mode
6=something to do with the quantization matrix
7=set navigation pack insertion for DVD: adds 0xbf (private stream 2)
packets to the MPEG. The size of these packets is 2048 bytes (including
the header of 6 bytes: 0x000001bf + length). The payload is zeroed and
it is up to the application to fill them in. These packets are apparently
inserted every four frames.
8=enable scene change detection (seems to be a failure)
9=set history parameters of the video input module
10=set input field order of VIM
11=set quantization matrix
12=reset audio interface after channel change or input switch (has no argument).
Needed for the cx2584x, not needed for the mspx4xx, but it doesn't seem to
do any harm calling it regardless.
13=set audio volume delay
14=set audio delay
Param[1]
^^^^^^^^
Command value.
Decoder playback 시작, 정지와 속도
2201-2365Decoder API도 decoder firmware에 속하므로 `cx23415` 전용입니다. `PING_FW`(0/0x00)는 응답 확인, `START_PLAYBACK`(1/0x01)은 시작 또는 재개, `STOP_PLAYBACK`(2/0x02)은 buffer를 비우며 재생을 종료합니다.
필드의미
START Param[0]GOP 안의 0-based 시작 frame
STOP Param[0]0=마지막 frame 유지, 1=즉시 black
STOP Param[1:2]정지할 33비트 PTS low/high; 0이면 즉시
SPEED Param[0] bits0:70=normal, 1=1.5x, n=n배 fast 또는 1/n slow; n은 실질적으로 2까지
SPEED Param[0] bit30/311.5x frame-drop 방식과 slow/fast 방향
SPEED Param[1]0=forward, 1=reverse
SPEED Param[2:6]I/P/B mask, reverse GOP의 B 수, audio mute, frame/field 표시, 미구현 muted audio frame 수
Smooth mode에서는 host가 전체 stream을 보내고 firmware가 frame을 버리며, coarse mode에서는 host가 index를 사용해 필요한 frame만 보냅니다. reverse playback은 완전한 GOP를 역순으로 써야 하고 picture mask는 I 또는 I/P로 제한해야 합니다. B frame을 포함하면 영상이 손상됩니다.
Decoder firmware API description
--------------------------------
.. note:: this API is part of the decoder firmware, so it's cx23415 only.
CX2341X_DEC_PING_FW
~~~~~~~~~~~~~~~~~~~
Enum: 0/0x00
Description
^^^^^^^^^^^
This API call does nothing. It may be used to check if the firmware
is responding.
CX2341X_DEC_START_PLAYBACK
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 1/0x01
Description
^^^^^^^^^^^
Begin or resume playback.
Param[0]
^^^^^^^^
0 based frame number in GOP to begin playback from.
Param[1]
^^^^^^^^
Specifies the number of muted audio frames to play before normal
audio resumes. (This is not implemented in the firmware, leave at 0)
CX2341X_DEC_STOP_PLAYBACK
~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 2/0x02
Description
^^^^^^^^^^^
Ends playback and clears all decoder buffers. If PTS is not zero,
playback stops at specified PTS.
Param[0]
^^^^^^^^
Display 0=last frame, 1=black
.. note::
this takes effect immediately, so if you want to wait for a PTS,
then use '0', otherwise the screen goes to black at once.
You can call this later (even if there is no playback) with a 1 value
to set the screen to black.
Param[1]
^^^^^^^^
PTS low
Param[2]
^^^^^^^^
PTS high
CX2341X_DEC_SET_PLAYBACK_SPEED
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 3/0x03
Description
^^^^^^^^^^^
Playback stream at speed other than normal. There are two modes of
operation:
- Smooth: host transfers entire stream and firmware drops unused
frames.
- Coarse: host drops frames based on indexing as required to achieve
desired speed.
Param[0]
^^^^^^^^
.. code-block:: none
Bitmap:
0:7 0 normal
1 fast only "1.5 times"
n nX fast, 1/nX slow
30 Framedrop:
'0' during 1.5 times play, every other B frame is dropped
'1' during 1.5 times play, stream is unchanged (bitrate
must not exceed 8mbps)
31 Speed:
'0' slow
'1' fast
.. note::
n is limited to 2. Anything higher does not result in
faster playback. Instead the host should start dropping frames.
Param[1]
^^^^^^^^
Direction: 0=forward, 1=reverse
.. note::
to make reverse playback work you have to write full GOPs in
reverse order.
Param[2]
^^^^^^^^
.. code-block:: none
Picture mask:
1=I frames
3=I, P frames
7=I, P, B frames
Param[3]
^^^^^^^^
B frames per GOP (for reverse play only)
.. note::
for reverse playback the Picture Mask should be set to I or I, P.
Adding B frames to the mask will result in corrupt video. This field
has to be set to the correct value in order to keep the timing correct.
Param[4]
^^^^^^^^
Mute audio: 0=disable, 1=enable
Param[5]
^^^^^^^^
Display 0=frame, 1=field
Param[6]
^^^^^^^^
Specifies the number of muted audio frames to play before normal audio
resumes. (Not implemented in the firmware, leave at 0)
Decoder step과 host-to-card DMA
2366-2484CommandEnumParameter 또는 Result
CX2341X_DEC_STEP_VIDEO5/0x050=frame, 1=top field, 2=bottom field 단위로 한 단계 진행
CX2341X_DEC_SET_DMA_BLOCK_SIZE8/0x08기본 transfer byte 크기; 실제 command에서 다른 크기 가능
CX2341X_DEC_GET_XFER_INFO9/0x09stream type, address offset, 최대 transfer byte, buffer fullness; EOS 감지
CX2341X_DEC_GET_DMA_STATUS10/0x0Abit1 완료, bit2 DMA 오류, bit3 linked-list 오류; type 0=MPEG, 1=OSD, 2=YUV
CX2341X_DEC_SCHED_DMA_FROM_HOST11/0x0Blinked list 주소, 총 byte 수, DMA type
decoder DMA는 encoder의 `0xC9`와 `0xCC`에 대응해 반대 방향으로 동작합니다. `GET_XFER_INFO`의 buffer fullness와 최대 전송량을 사용하면 end-of-stream 상태를 판단할 수 있습니다.
CX2341X_DEC_STEP_VIDEO
~~~~~~~~~~~~~~~~~~~~~~
Enum: 5/0x05
Description
^^^^^^^^^^^
Each call to this API steps the playback to the next unit defined below
in the current playback direction.
Param[0]
^^^^^^^^
0=frame, 1=top field, 2=bottom field
CX2341X_DEC_SET_DMA_BLOCK_SIZE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 8/0x08
Description
^^^^^^^^^^^
Set DMA transfer block size. Counterpart to API 0xC9
Param[0]
^^^^^^^^
DMA transfer block size in bytes. A different size may be specified
when issuing the DMA transfer command.
CX2341X_DEC_GET_XFER_INFO
~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 9/0x09
Description
^^^^^^^^^^^
This API call may be used to detect an end of stream condition.
Result[0]
^^^^^^^^^
Stream type
Result[1]
^^^^^^^^^
Address offset
Result[2]
^^^^^^^^^
Maximum bytes to transfer
Result[3]
^^^^^^^^^
Buffer fullness
CX2341X_DEC_GET_DMA_STATUS
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 10/0x0A
Description
^^^^^^^^^^^
Status of the last DMA transfer
Result[0]
^^^^^^^^^
Bit 1 set means transfer complete
Bit 2 set means DMA error
Bit 3 set means linked list error
Result[1]
^^^^^^^^^
DMA type: 0=MPEG, 1=OSD, 2=YUV
CX2341X_DEC_SCHED_DMA_FROM_HOST
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 11/0x0B
Description
^^^^^^^^^^^
Setup DMA from host operation. Counterpart to API 0xCC
Param[0]
^^^^^^^^
Memory address of link list
Param[1]
^^^^^^^^
Total # of bytes to transfer
Param[2]
^^^^^^^^
DMA type (0=MPEG, 1=OSD, 2=YUV)
Decoder pause, standard와 timing
2485-2607CommandEnum의미
CX2341X_DEC_PAUSE_PLAYBACK13/0x0D즉시 freeze; 0=last frame, 1=black
CX2341X_DEC_HALT_FW14/0x0Efirmware 중지; upload 전까지 API 불가
CX2341X_DEC_SET_STANDARD16/0x100=NTSC, 1=PAL
CX2341X_DEC_GET_VERSION17/0x11build/minor/major bitmask
CX2341X_DEC_SET_STREAM_INPUT20/0x140=memory, 1=streaming
CX2341X_DEC_GET_TIMING_INFO21/0x15decode-order frame count, display-order 33비트 video PTS와 SCR
pause 상태에서 내부 buffer가 가득 차면 더는 data를 받지 않고 data request IRQ를 mask합니다. timing result의 video PTS와 SCR은 각각 하위 32비트 word와 bit32 word를 결합해야 합니다.
CX2341X_DEC_PAUSE_PLAYBACK
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 13/0x0D
Description
^^^^^^^^^^^
Freeze playback immediately. In this mode, when internal buffers are
full, no more data will be accepted and data request IRQs will be
masked.
Param[0]
^^^^^^^^
Display: 0=last frame, 1=black
CX2341X_DEC_HALT_FW
~~~~~~~~~~~~~~~~~~~
Enum: 14/0x0E
Description
^^^^^^^^^^^
The firmware is halted and no further API calls are serviced until
the firmware is uploaded again.
CX2341X_DEC_SET_STANDARD
~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 16/0x10
Description
^^^^^^^^^^^
Selects display standard
Param[0]
^^^^^^^^
0=NTSC, 1=PAL
CX2341X_DEC_GET_VERSION
~~~~~~~~~~~~~~~~~~~~~~~
Enum: 17/0x11
Description
^^^^^^^^^^^
Returns decoder firmware version information
Result[0]
^^^^^^^^^
Version bitmask:
- Bits 0:15 build
- Bits 16:23 minor
- Bits 24:31 major
CX2341X_DEC_SET_STREAM_INPUT
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 20/0x14
Description
^^^^^^^^^^^
Select decoder stream input port
Param[0]
^^^^^^^^
0=memory (default), 1=streaming
CX2341X_DEC_GET_TIMING_INFO
~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 21/0x15
Description
^^^^^^^^^^^
Returns timing information from start of playback
Result[0]
^^^^^^^^^
Frame count by decode order
Result[1]
^^^^^^^^^
Video PTS bits 0:31 by display order
Result[2]
^^^^^^^^^
Video PTS bit 32 by display order
Result[3]
^^^^^^^^^
SCR bits 0:31 by display order
Result[4]
^^^^^^^^^
SCR bit 32 by display order
Decoder audio, event, VBI와 prebuffer
2608-2762CommandEnumParameter 또는 Result
CX2341X_DEC_SET_AUDIO_MODE22/0x16dual-mono와 stereo 각각 Stereo/Left/Right/Mono/Swap/-1 unchanged
CX2341X_DEC_SET_EVENT_NOTIFICATION23/0x17audio mode change, decoder start, 미상 event 4, frame sync event 5
CX2341X_DEC_SET_DISPLAY_BUFFERS24/0x180=6개, 1=9개; reverse에서 모든 frame decode하려면 9개
CX2341X_DEC_EXTRACT_VBI25/0x19extension/user 또는 private packet에서 VBI 추출; table 위치와 크기 반환
CX2341X_DEC_SET_DECODER_SOURCE26/0x1A0=host MPEG, 1=encoder YUV, 2=host YUV; width/height/audio bitmap
CX2341X_DEC_SET_PREBUFFERING30/0x1E0=off, 1=on; <8 Mbps는 128 KiB, >8 Mbps는 640 KiB까지
decoder source의 width, height와 audio property bitmap은 encoder 설정과 일치해야 합니다. event notification은 encoder `0xD5`의 대응 command이며 interrupt bit와 mailbox slot을 함께 지정합니다.
CX2341X_DEC_SET_AUDIO_MODE
~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 22/0x16
Description
^^^^^^^^^^^
Select audio mode
Param[0]
^^^^^^^^
Dual mono mode action
0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
Param[1]
^^^^^^^^
Stereo mode action:
0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
CX2341X_DEC_SET_EVENT_NOTIFICATION
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 23/0x17
Description
^^^^^^^^^^^
Setup firmware to notify the host about a particular event.
Counterpart to API 0xD5
Param[0]
^^^^^^^^
Event:
- 0=Audio mode change between mono, (joint) stereo and dual channel.
- 3=Decoder started
- 4=Unknown: goes off 10-15 times per second while decoding.
- 5=Some sync event: goes off once per frame.
Param[1]
^^^^^^^^
Notification 0=disabled, 1=enabled
Param[2]
^^^^^^^^
Interrupt bit
Param[3]
^^^^^^^^
Mailbox slot, -1 if no mailbox required.
CX2341X_DEC_SET_DISPLAY_BUFFERS
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 24/0x18
Description
^^^^^^^^^^^
Number of display buffers. To decode all frames in reverse playback you
must use nine buffers.
Param[0]
^^^^^^^^
0=six buffers, 1=nine buffers
CX2341X_DEC_EXTRACT_VBI
~~~~~~~~~~~~~~~~~~~~~~~
Enum: 25/0x19
Description
^^^^^^^^^^^
Extracts VBI data
Param[0]
^^^^^^^^
0=extract from extension & user data, 1=extract from private packets
Result[0]
^^^^^^^^^
VBI table location
Result[1]
^^^^^^^^^
VBI table size
CX2341X_DEC_SET_DECODER_SOURCE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 26/0x1A
Description
^^^^^^^^^^^
Selects decoder source. Ensure that the parameters passed to this
API match the encoder settings.
Param[0]
^^^^^^^^
Mode: 0=MPEG from host, 1=YUV from encoder, 2=YUV from host
Param[1]
^^^^^^^^
YUV picture width
Param[2]
^^^^^^^^
YUV picture height
Param[3]
^^^^^^^^
Bitmap: see Param[0] of API 0xBD
CX2341X_DEC_SET_PREBUFFERING
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Enum: 30/0x1E
Description
^^^^^^^^^^^
Decoder prebuffering, when enabled up to 128KB are buffered for
streams <8mpbs or 640KB for streams >8mbps
Param[0]
^^^^^^^^
0=off, 1=on
PVR350 register 개요와 horizontal filter
2763-2941이 register 목록은 시행착오로 작성된 v0.4 역공학 자료입니다. 일부 register는 서로 의존하거나 특정 적재 순서가 필요하며, 잘못된 값을 쓰면 firmware reload 또는 hardware reset이 필요할 수 있습니다. 크기 필드에 0을 쓰는 것도 일반적으로 위험합니다.
주소의미
2800decoder enable
2804-2818Y horizontal alias filter 5개 값 + trigger; 16회 programming
281C-2830UV horizontal alias filter 5개 값 + trigger; 16회 programming
2834/2838Y/UV source와 destination width
283C-2868Y/UV horizontal scaling 보조값
2854horizontal scaling master
alias filter는 값 register를 모두 쓴 뒤 trigger를 접근해야 data가 clock됩니다. Y와 UV 모두 firmware lookup table의 설정을 사용하고 전체 절차를 16회 반복합니다.
확대 시 master는 `(source_width * 0x00200000) / destination_width`이고 divider는 없음입니다. 1/2 이하 축소는 source width를 2 또는 4로 나눈 값으로 계산하고 divider를 2 또는 4로 맞춥니다. 결과는 항상 올림합니다.
PVR350 Video decoder registers 0x02002800 -> 0x02002B00
-------------------------------------------------------
Author: Ian Armstrong <ian@iarmst.demon.co.uk>
Version: v0.4
Date: 12 March 2007
This list has been worked out through trial and error. There will be mistakes
and omissions. Some registers have no obvious effect so it's hard to say what
they do, while others interact with each other, or require a certain load
sequence. Horizontal filter setup is one example, with six registers working
in unison and requiring a certain load sequence to correctly configure. The
indexed colour palette is much easier to set at just two registers, but again
it requires a certain load sequence.
Some registers are fussy about what they are set to. Load in a bad value & the
decoder will fail. A firmware reload will often recover, but sometimes a reset
is required. For registers containing size information, setting them to 0 is
generally a bad idea. For other control registers i.e. 2878, you'll only find
out what values are bad when it hangs.
.. code-block:: none
--------------------------------------------------------------------------------
2800
bit 0
Decoder enable
0 = disable
1 = enable
--------------------------------------------------------------------------------
2804
bits 0:31
Decoder horizontal Y alias register 1
---------------
2808
bits 0:31
Decoder horizontal Y alias register 2
---------------
280C
bits 0:31
Decoder horizontal Y alias register 3
---------------
2810
bits 0:31
Decoder horizontal Y alias register 4
---------------
2814
bits 0:31
Decoder horizontal Y alias register 5
---------------
2818
bits 0:31
Decoder horizontal Y alias trigger
These six registers control the horizontal aliasing filter for the Y plane.
The first five registers must all be loaded before accessing the trigger
(2818), as this register actually clocks the data through for the first
five.
To correctly program set the filter, this whole procedure must be done 16
times. The actual register contents are copied from a lookup-table in the
firmware which contains 4 different filter settings.
--------------------------------------------------------------------------------
281C
bits 0:31
Decoder horizontal UV alias register 1
---------------
2820
bits 0:31
Decoder horizontal UV alias register 2
---------------
2824
bits 0:31
Decoder horizontal UV alias register 3
---------------
2828
bits 0:31
Decoder horizontal UV alias register 4
---------------
282C
bits 0:31
Decoder horizontal UV alias register 5
---------------
2830
bits 0:31
Decoder horizontal UV alias trigger
These six registers control the horizontal aliasing for the UV plane.
Operation is the same as the Y filter, with 2830 being the trigger
register.
--------------------------------------------------------------------------------
2834
bits 0:15
Decoder Y source width in pixels
bits 16:31
Decoder Y destination width in pixels
---------------
2838
bits 0:15
Decoder UV source width in pixels
bits 16:31
Decoder UV destination width in pixels
NOTE: For both registers, the resulting image must be fully visible on
screen. If the image exceeds the right edge both the source and destination
size must be adjusted to reflect the visible portion. For the source width,
you must take into account the scaling when calculating the new value.
--------------------------------------------------------------------------------
283C
bits 0:31
Decoder Y horizontal scaling
Normally = Reg 2854 >> 2
---------------
2840
bits 0:31
Decoder ?? unknown - horizontal scaling
Usually 0x00080514
---------------
2844
bits 0:31
Decoder UV horizontal scaling
Normally = Reg 2854 >> 2
---------------
2848
bits 0:31
Decoder ?? unknown - horizontal scaling
Usually 0x00100514
---------------
284C
bits 0:31
Decoder ?? unknown - Y plane
Usually 0x00200020
---------------
2850
bits 0:31
Decoder ?? unknown - UV plane
Usually 0x00200020
---------------
2854
bits 0:31
Decoder 'master' value for horizontal scaling
---------------
2858
bits 0:31
Decoder ?? unknown
Usually 0
---------------
285C
bits 0:31
Decoder ?? unknown
Normally = Reg 2854 >> 1
---------------
2860
bits 0:31
Decoder ?? unknown
Usually 0
---------------
2864
bits 0:31
Decoder ?? unknown
Normally = Reg 2854 >> 1
---------------
2868
bits 0:31
Decoder ?? unknown
Usually 0
Most of these registers either control horizontal scaling, or appear linked
to it in some way. Register 2854 contains the 'master' value & the other
registers can be calculated from that one. You must also remember to
correctly set the divider in Reg 2874.Horizontal offset, 화면 timing과 출력 영역
2942-3134주소bitfield와 의미
286CY/UV video buffer horizontal offset
2870Y/UV actual output offset; 값이 클수록 왼쪽 이동
2874Y bits0:1, UV bits4:5 output divider; bit16 horizontal filter disable
2878bit1 OSD, bit2 NTSC/PAL, bit5 field swap
287C전체 화면 horizontal 이동과 timing
2888field alignment 관련 미상 제어; 금지값은 reload 필요
288COSD 위치 안정성 관련 미상 값
2890video output을 오른쪽으로 이동
2894/2898surround/window YUV 색, video on/off와 plane/UV byte order
289C두 field의 vertical alignment
28A0decoder/OSD 최대 width와 height
video window가 오른쪽 경계를 넘으면 source와 destination width를 실제 표시 범위에 맞춰 함께 줄여야 하고 source 값에는 scaling을 반영해야 합니다. `2890`으로 오른쪽 이동할 때도 경계를 넘으면 영상이 손상됩니다.
`2898`은 bit24로 video를 끄고 bit28로 Y/UV plane 순서를, bit29로 두 번째 plane의 UV/VU byte order를 바꿉니다. 일반적으로 첫 plane은 Y, 두 번째는 UV입니다.
To enlarge:
Reg 2854 = (source_width * 0x00200000) / destination_width
Reg 2874 = No divide
To reduce from full size down to half size:
Reg 2854 = (source_width/2 * 0x00200000) / destination width
Reg 2874 = Divide by 2
To reduce from half size down to quarter size:
Reg 2854 = (source_width/4 * 0x00200000) / destination width
Reg 2874 = Divide by 4
The result is always rounded up.
--------------------------------------------------------------------------------
286C
bits 0:15
Decoder horizontal Y buffer offset
bits 15:31
Decoder horizontal UV buffer offset
Offset into the video image buffer. If the offset is gradually incremented,
the on screen image will move left & wrap around higher up on the right.
--------------------------------------------------------------------------------
2870
bits 0:15
Decoder horizontal Y output offset
bits 16:31
Decoder horizontal UV output offset
Offsets the actual video output. Controls output alignment of the Y & UV
planes. The higher the value, the greater the shift to the left. Use
reg 2890 to move the image right.
--------------------------------------------------------------------------------
2874
bits 0:1
Decoder horizontal Y output size divider
00 = No divide
01 = Divide by 2
10 = Divide by 3
bits 4:5
Decoder horizontal UV output size divider
00 = No divide
01 = Divide by 2
10 = Divide by 3
bit 8
Decoder ?? unknown
0 = Normal
1 = Affects video output levels
bit 16
Decoder ?? unknown
0 = Normal
1 = Disable horizontal filter
--------------------------------------------------------------------------------
2878
bit 0
?? unknown
bit 1
osd on/off
0 = osd off
1 = osd on
bit 2
Decoder + osd video timing
0 = NTSC
1 = PAL
bits 3:4
?? unknown
bit 5
Decoder + osd
Swaps upper & lower fields
--------------------------------------------------------------------------------
287C
bits 0:10
Decoder & osd ?? unknown
Moves entire screen horizontally. Starts at 0x005 with the screen
shifted heavily to the right. Incrementing in steps of 0x004 will
gradually shift the screen to the left.
bits 11:31
?? unknown
Normally contents are 0x00101111 (NTSC) or 0x1010111d (PAL)
--------------------------------------------------------------------------------
2880 -------- ?? unknown
2884 -------- ?? unknown
--------------------------------------------------------------------------------
2888
bit 0
Decoder + osd ?? unknown
0 = Normal
1 = Misaligned fields (Correctable through 289C & 28A4)
bit 4
?? unknown
bit 8
?? unknown
Warning: Bad values will require a firmware reload to recover.
Known to be bad are 0x000,0x011,0x100,0x111
--------------------------------------------------------------------------------
288C
bits 0:15
osd ?? unknown
Appears to affect the osd position stability. The higher the value the
more unstable it becomes. Decoder output remains stable.
bits 16:31
osd ?? unknown
Same as bits 0:15
--------------------------------------------------------------------------------
2890
bits 0:11
Decoder output horizontal offset.
Horizontal offset moves the video image right. A small left shift is
possible, but it's better to use reg 2870 for that due to its greater
range.
NOTE: Video corruption will occur if video window is shifted off the right
edge. To avoid this read the notes for 2834 & 2838.
--------------------------------------------------------------------------------
2894
bits 0:23
Decoder output video surround colour.
Contains the colour (in yuv) used to fill the screen when the video is
running in a window.
--------------------------------------------------------------------------------
2898
bits 0:23
Decoder video window colour
Contains the colour (in yuv) used to fill the video window when the
video is turned off.
bit 24
Decoder video output
0 = Video on
1 = Video off
bit 28
Decoder plane order
0 = Y,UV
1 = UV,Y
bit 29
Decoder second plane byte order
0 = Normal (UV)
1 = Swapped (VU)
In normal usage, the first plane is Y & the second plane is UV. Though the
order of the planes can be swapped, only the byte order of the second plane
can be swapped. This isn't much use for the Y plane, but can be useful for
the UV plane.
--------------------------------------------------------------------------------
289C
bits 0:15
Decoder vertical field offset 1
bits 16:31
Decoder vertical field offset 2
Controls field output vertical alignment. The higher the number, the lower
the image on screen. Known starting values are 0x011E0017 (NTSC) &
0x01500017 (PAL)
--------------------------------------------------------------------------------
28A0
bits 0:15
Decoder & osd width in pixels
bits 16:31
Decoder & osd height in pixels
All output from the decoder & osd are disabled beyond this area. Decoder
output will simply go black outside of this region. If the osd tries to
exceed this area it will become corrupt.OSD alignment와 vertical filter
3135-3295주소의미
28A4OSD left shift; 0 또는 0x770..0x7FF만 안전
28A8OSD field별 vertical offset
28C0현재 field와 scanline
28FCbit0=1이면 decoder/OSD 출력 파손
2900-2908Y vertical alias 값 2개 + trigger; 16회 programming
290C-2914UV vertical alias 값 2개 + trigger; 16회 programming
2918/291CY/UV source와 destination height
2920-294CY/UV vertical scaling 값
2930vertical scaling master
vertical alias filter도 값 register를 먼저 쓰고 trigger를 접근하며 16회 반복합니다. 화면 아래 경계를 넘는 영상은 source와 destination height를 보이는 부분에 맞춰 조정하고 scaling을 계산에 반영해야 합니다.
vertical master 계산은 horizontal과 같은 구조입니다. 확대는 source height 전체, 절반 이하 축소는 source height를 2 또는 4로 나눠 `0x00200000`을 곱한 뒤 destination height로 나누며 `296C` divider와 일치시킵니다.
--------------------------------------------------------------------------------
28A4
bits 0:11
osd left shift.
Has a range of 0x770->0x7FF. With the exception of 0, any value outside of
this range corrupts the osd.
--------------------------------------------------------------------------------
28A8
bits 0:15
osd vertical field offset 1
bits 16:31
osd vertical field offset 2
Controls field output vertical alignment. The higher the number, the lower
the image on screen. Known starting values are 0x011E0017 (NTSC) &
0x01500017 (PAL)
--------------------------------------------------------------------------------
28AC -------- ?? unknown
|
V
28BC -------- ?? unknown
--------------------------------------------------------------------------------
28C0
bit 0
Current output field
0 = first field
1 = second field
bits 16:31
Current scanline
The scanline counts from the top line of the first field
through to the last line of the second field.
--------------------------------------------------------------------------------
28C4 -------- ?? unknown
|
V
28F8 -------- ?? unknown
--------------------------------------------------------------------------------
28FC
bit 0
?? unknown
0 = Normal
1 = Breaks decoder & osd output
--------------------------------------------------------------------------------
2900
bits 0:31
Decoder vertical Y alias register 1
---------------
2904
bits 0:31
Decoder vertical Y alias register 2
---------------
2908
bits 0:31
Decoder vertical Y alias trigger
These three registers control the vertical aliasing filter for the Y plane.
Operation is similar to the horizontal Y filter (2804). The only real
difference is that there are only two registers to set before accessing
the trigger register (2908). As for the horizontal filter, the values are
taken from a lookup table in the firmware, and the procedure must be
repeated 16 times to fully program the filter.
--------------------------------------------------------------------------------
290C
bits 0:31
Decoder vertical UV alias register 1
---------------
2910
bits 0:31
Decoder vertical UV alias register 2
---------------
2914
bits 0:31
Decoder vertical UV alias trigger
These three registers control the vertical aliasing filter for the UV
plane. Operation is the same as the Y filter, with 2914 being the trigger.
--------------------------------------------------------------------------------
2918
bits 0:15
Decoder Y source height in pixels
bits 16:31
Decoder Y destination height in pixels
---------------
291C
bits 0:15
Decoder UV source height in pixels divided by 2
bits 16:31
Decoder UV destination height in pixels
NOTE: For both registers, the resulting image must be fully visible on
screen. If the image exceeds the bottom edge both the source and
destination size must be adjusted to reflect the visible portion. For the
source height, you must take into account the scaling when calculating the
new value.
--------------------------------------------------------------------------------
2920
bits 0:31
Decoder Y vertical scaling
Normally = Reg 2930 >> 2
---------------
2924
bits 0:31
Decoder Y vertical scaling
Normally = Reg 2920 + 0x514
---------------
2928
bits 0:31
Decoder UV vertical scaling
When enlarging = Reg 2930 >> 2
When reducing = Reg 2930 >> 3
---------------
292C
bits 0:31
Decoder UV vertical scaling
Normally = Reg 2928 + 0x514
---------------
2930
bits 0:31
Decoder 'master' value for vertical scaling
---------------
2934
bits 0:31
Decoder ?? unknown - Y vertical scaling
---------------
2938
bits 0:31
Decoder Y vertical scaling
Normally = Reg 2930
---------------
293C
bits 0:31
Decoder ?? unknown - Y vertical scaling
---------------
2940
bits 0:31
Decoder UV vertical scaling
When enlarging = Reg 2930 >> 1
When reducing = Reg 2930
---------------
2944
bits 0:31
Decoder ?? unknown - UV vertical scaling
---------------
2948
bits 0:31
Decoder UV vertical scaling
Normally = Reg 2940
---------------
294C
bits 0:31
Decoder ?? unknown - UV vertical scaling
Most of these registers either control vertical scaling, or appear linked
to it in some way. Register 2930 contains the 'master' value & all other
registers can be calculated from that one. You must also remember to
correctly set the divider in Reg 296CVertical line index, offset와 divider
3296-3394주소bitfield와 의미
2950/2954첫째/둘째 field의 Y display-buffer line index와 line skip
2958/295C첫째/둘째 field의 UV display-buffer line index와 line skip
2960destination height-1과 destination height/2
2964둘째/첫째 field의 Y vertical offset; 값이 클수록 위로 이동
2968둘째/첫째 field의 UV vertical offset; 값이 클수록 위로 이동
296CY bits0:1, UV bits8:9 divider: 없음/2/4
2970bit0 output level 영향, bit16 vertical filter disable
2974-29EF기능 미상
Y와 UV plane은 field별 line index, line skip과 vertical offset을 따로 가집니다. master scaling 값과 `296C` divider를 함께 맞추지 않으면 크기와 field alignment가 어긋납니다.
To enlarge:
Reg 2930 = (source_height * 0x00200000) / destination_height
Reg 296C = No divide
To reduce from full size down to half size:
Reg 2930 = (source_height/2 * 0x00200000) / destination height
Reg 296C = Divide by 2
To reduce from half down to quarter.
Reg 2930 = (source_height/4 * 0x00200000) / destination height
Reg 296C = Divide by 4
--------------------------------------------------------------------------------
2950
bits 0:15
Decoder Y line index into display buffer, first field
bits 16:31
Decoder Y vertical line skip, first field
--------------------------------------------------------------------------------
2954
bits 0:15
Decoder Y line index into display buffer, second field
bits 16:31
Decoder Y vertical line skip, second field
--------------------------------------------------------------------------------
2958
bits 0:15
Decoder UV line index into display buffer, first field
bits 16:31
Decoder UV vertical line skip, first field
--------------------------------------------------------------------------------
295C
bits 0:15
Decoder UV line index into display buffer, second field
bits 16:31
Decoder UV vertical line skip, second field
--------------------------------------------------------------------------------
2960
bits 0:15
Decoder destination height minus 1
bits 16:31
Decoder destination height divided by 2
--------------------------------------------------------------------------------
2964
bits 0:15
Decoder Y vertical offset, second field
bits 16:31
Decoder Y vertical offset, first field
These two registers shift the Y plane up. The higher the number, the
greater the shift.
--------------------------------------------------------------------------------
2968
bits 0:15
Decoder UV vertical offset, second field
bits 16:31
Decoder UV vertical offset, first field
These two registers shift the UV plane up. The higher the number, the
greater the shift.
--------------------------------------------------------------------------------
296C
bits 0:1
Decoder vertical Y output size divider
00 = No divide
01 = Divide by 2
10 = Divide by 4
bits 8:9
Decoder vertical UV output size divider
00 = No divide
01 = Divide by 2
10 = Divide by 4
--------------------------------------------------------------------------------
2970
bit 0
Decoder ?? unknown
0 = Normal
1 = Affect video output levels
bit 16
Decoder ?? unknown
0 = Normal
1 = Disable vertical filter
--------------------------------------------------------------------------------
2974 -------- ?? unknown
|
V
29EF -------- ?? unknown
--------------------------------------------------------------------------------OSD color, 좌표, palette와 filter
3395-3586주소의미
2A00color mode, display bpp, global/local alpha, color key, ARGB/AYVU
2A04/2A08visible rectangle의 left/top과 right/bottom
2A0COSD buffer index
2A1032비트 word 단위 buffer width
2A14pixel height와 buffer line index
2A18transparent color key
2A1C8-bit global alpha
2A30/2A34indexed palette index와 새 color; index 0x00..0xFF
2A40-2A54brightness/tint/color shift 관련 미상 제어
2B00bit0 OSD filter on/off
8 bpp에서는 color mode와 무관하게 indexed color입니다. 16/32 bpp에서 선택한 color depth가 할당 byte보다 작으면 남는 byte는 padding입니다. 565/555/444의 color key는 항상 16비트이며 key 값은 `2A18`에 씁니다.
32 bpp와 indexed8의 local alpha는 pixel당 0=transparent, 255=solid의 256단계입니다. 555/444의 남는 bit는 0=solid, 1=fully transparent인 switch이고 565에는 local alpha가 없습니다. global alpha는 OSD 전체에 0..255로 적용되며 color key·local·global alpha를 함께 사용할 수 있습니다.
좌표 register는 OSD 자체 크기가 아니라 위치와 보이는 범위를 정합니다. 오른쪽 display 경계를 넘으면 OSD가 손상됩니다. palette는 먼저 `2A30`에 index를 쓰고 `2A34`에 새 color를 써야 합니다.
2A00
bits 0:2
osd colour mode
000 = 8 bit indexed
001 = 16 bit (565)
010 = 15 bit (555)
011 = 12 bit (444)
100 = 32 bit (8888)
bits 4:5
osd display bpp
01 = 8 bit
10 = 16 bit
11 = 32 bit
bit 8
osd global alpha
0 = Off
1 = On
bit 9
osd local alpha
0 = Off
1 = On
bit 10
osd colour key
0 = Off
1 = On
bit 11
osd ?? unknown
Must be 1
bit 13
osd colour space
0 = ARGB
1 = AYVU
bits 16:31
osd ?? unknown
Must be 0x001B (some kind of buffer pointer ?)
When the bits-per-pixel is set to 8, the colour mode is ignored and
assumed to be 8 bit indexed. For 16 & 32 bits-per-pixel the colour depth
is honoured, and when using a colour depth that requires fewer bytes than
allocated the extra bytes are used as padding. So for a 32 bpp with 8 bit
index colour, there are 3 padding bytes per pixel. It's also possible to
select 16bpp with a 32 bit colour mode. This results in the pixel width
being doubled, but the color key will not work as expected in this mode.
Colour key is as it suggests. You designate a colour which will become
completely transparent. When using 565, 555 or 444 colour modes, the
colour key is always 16 bits wide. The colour to key on is set in Reg 2A18.
Local alpha works differently depending on the colour mode. For 32bpp & 8
bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being
transparent and 255 being solid. For the 16bpp modes 555 & 444, the unused
bit(s) act as a simple transparency switch, with 0 being solid & 1 being
fully transparent. There is no local alpha support for 16bit 565.
Global alpha is a 256 step transparency that applies to the entire osd,
with 0 being transparent & 255 being solid.
It's possible to combine colour key, local alpha & global alpha.
--------------------------------------------------------------------------------
2A04
bits 0:15
osd x coord for left edge
bits 16:31
osd y coord for top edge
---------------
2A08
bits 0:15
osd x coord for right edge
bits 16:31
osd y coord for bottom edge
For both registers, (0,0) = top left corner of the display area. These
registers do not control the osd size, only where it's positioned & how
much is visible. The visible osd area cannot exceed the right edge of the
display, otherwise the osd will become corrupt. See reg 2A10 for
setting osd width.
--------------------------------------------------------------------------------
2A0C
bits 0:31
osd buffer index
An index into the osd buffer. Slowly incrementing this moves the osd left,
wrapping around onto the right edge
--------------------------------------------------------------------------------
2A10
bits 0:11
osd buffer 32 bit word width
Contains the width of the osd measured in 32 bit words. This means that all
colour modes are restricted to a byte width which is divisible by 4.
--------------------------------------------------------------------------------
2A14
bits 0:15
osd height in pixels
bits 16:32
osd line index into buffer
osd will start displaying from this line.
--------------------------------------------------------------------------------
2A18
bits 0:31
osd colour key
Contains the colour value which will be transparent.
--------------------------------------------------------------------------------
2A1C
bits 0:7
osd global alpha
Contains the global alpha value (equiv ivtvfbctl --alpha XX)
--------------------------------------------------------------------------------
2A20 -------- ?? unknown
|
V
2A2C -------- ?? unknown
--------------------------------------------------------------------------------
2A30
bits 0:7
osd colour to change in indexed palette
---------------
2A34
bits 0:31
osd colour for indexed palette
To set the new palette, first load the index of the colour to change into
2A30, then load the new colour into 2A34. The full palette is 256 colours,
so the index range is 0x00-0xFF
--------------------------------------------------------------------------------
2A38 -------- ?? unknown
2A3C -------- ?? unknown
--------------------------------------------------------------------------------
2A40
bits 0:31
osd ?? unknown
Affects overall brightness, wrapping around to black
--------------------------------------------------------------------------------
2A44
bits 0:31
osd ?? unknown
Green tint
--------------------------------------------------------------------------------
2A48
bits 0:31
osd ?? unknown
Red tint
--------------------------------------------------------------------------------
2A4C
bits 0:31
osd ?? unknown
Affects overall brightness, wrapping around to black
--------------------------------------------------------------------------------
2A50
bits 0:31
osd ?? unknown
Colour shift
--------------------------------------------------------------------------------
2A54
bits 0:31
osd ?? unknown
Colour shift
--------------------------------------------------------------------------------
2A58 -------- ?? unknown
|
V
2AFC -------- ?? unknown
--------------------------------------------------------------------------------
2B00
bit 0
osd filter control
0 = filter off
1 = filter on
bits 1:4
osd ?? unknown
--------------------------------------------------------------------------------
cx2341x DMA engine과 scatter-gather
3587-3685절 제목은 원문에서 `cx231xx DMA engine`이라고 쓰지만 본문과 대상 hardware는 `cx2341x`입니다. 표기 차이를 숨기지 않고 원문을 그대로 보존합니다.
cx2341x PCI interface는 bus master DMA를 지원합니다. 큰 연속 physical memory를 구하기 어려운 virtual-memory 환경에서는 여러 작은 buffer를 하나의 transfer로 연결하는 scatter-gather를 사용합니다. 관찰된 평균 전송은 약 80 KiB이고 시작 시 128 KiB를 넘기도 하므로, 작은 block과 S-G 사용이 권장됩니다.
순서작업
1card가 Encoder interrupt 발생
2driver가 Mailbox #10에서 type, offset, size 읽음
3필요한 free DMA buffer로 scatter-gather array 구성
4ScheduleDMAtoHost API로 transfer 예약
5card가 DMA Complete interrupt 발생
6DMA status register 오류 확인
7새 buffer 후처리
Mailbox #10의 Result[0]은 type(확인된 값 0=MPEG), Result[1]은 card memory 상대 offset, Result[2]는 정확한 byte 수입니다. Encoder와 DMA Complete interrupt는 이전 transfer 종료와 다음 transfer 시작이 겹치면 동시에 발생할 수 있습니다.
각 S-G element는 32비트 source address, 32비트 destination address, 마지막 word의 하위 18비트 byte count와 high-bit last flag로 구성됩니다. count는 256의 배수여야 하며 last flag를 빠뜨리면 DMA_DONE interrupt가 없고 stream이 손상될 가능성이 큽니다.
비트의미
0read completed
1write completed
2DMA read error
3DMA write error
4scatter-gather array error
The cx231xx DMA engine
----------------------
This page describes the structures and procedures used by the cx2341x DMA
engine.
Introduction
~~~~~~~~~~~~
The cx2341x PCI interface is busmaster capable. This means it has a DMA
engine to efficiently transfer large volumes of data between the card and main
memory without requiring help from a CPU. Like most hardware, it must operate
on contiguous physical memory. This is difficult to come by in large quantities
on virtual memory machines.
Therefore, it also supports a technique called "scatter-gather". The card can
transfer multiple buffers in one operation. Instead of allocating one large
contiguous buffer, the driver can allocate several smaller buffers.
In practice, I've seen the average transfer to be roughly 80K, but transfers
above 128K were not uncommon, particularly at startup. The 128K figure is
important, because that is the largest block that the kernel can normally
allocate. Even still, 128K blocks are hard to come by, so the driver writer is
urged to choose a smaller block size and learn the scatter-gather technique.
Mailbox #10 is reserved for DMA transfer information.
Note: the hardware expects little-endian data ('intel format').
Flow
~~~~
This section describes, in general, the order of events when handling DMA
transfers. Detailed information follows this section.
- The card raises the Encoder interrupt.
- The driver reads the transfer type, offset and size from Mailbox #10.
- The driver constructs the scatter-gather array from enough free dma buffers
to cover the size.
- The driver schedules the DMA transfer via the ScheduleDMAtoHost API call.
- The card raises the DMA Complete interrupt.
- The driver checks the DMA status register for any errors.
- The driver post-processes the newly transferred buffers.
NOTE! It is possible that the Encoder and DMA Complete interrupts get raised
simultaneously. (End of the last, start of the next, etc.)
Mailbox #10
~~~~~~~~~~~
The Flags, Command, Return Value and Timeout fields are ignored.
- Name: Mailbox #10
- Results[0]: Type: 0: MPEG.
- Results[1]: Offset: The position relative to the card's memory space.
- Results[2]: Size: The exact number of bytes to transfer.
My speculation is that since the StartCapture API has a capture type of "RAW"
available, that the type field will have other values that correspond to YUV
and PCM data.
Scatter-Gather Array
~~~~~~~~~~~~~~~~~~~~
The scatter-gather array is a contiguously allocated block of memory that
tells the card the source and destination of each data-block to transfer.
Card "addresses" are derived from the offset supplied by Mailbox #10. Host
addresses are the physical memory location of the target DMA buffer.
Each S-G array element is a struct of three 32-bit words. The first word is
the source address, the second is the destination address. Both take up the
entire 32 bits. The lowest 18 bits of the third word is the transfer byte
count. The high-bit of the third word is the "last" flag. The last-flag tells
the card to raise the DMA_DONE interrupt. From hard personal experience, if
you forget to set this bit, the card will still "work" but the stream will
most likely get corrupted.
The transfer count must be a multiple of 256. Therefore, the driver will need
to track how much data in the target buffer is valid and deal with it
accordingly.
Array Element:
- 32-bit Source Address
- 32-bit Destination Address
- 14-bit reserved (high bit is the last flag)
- 18-bit byte count
DMA Transfer Status
~~~~~~~~~~~~~~~~~~~
Register 0x0004 holds the DMA Transfer Status:
- bit 0: read completed
- bit 1: write completed
- bit 2: DMA read error
- bit 3: DMA write error
- bit 4: Scatter-Gather array error
요약과 해설
cx2341x-devel.rst:1-3685이 문서는 cx2341x 계열의 공개되지 않은 hardware/firmware interface를 역공학한 개발 자료입니다. BAR0 memory map과 초기화 순서, 20개 mailbox의 호출 protocol, cx23415 전용 OSD·decoder API, encoder API, PVR350 display register와 DMA scatter-gather 형식을 한 문서에서 연결합니다.
API enum, parameter 순서, register bit와 source path는 ABI처럼 취급해야 합니다. 확정되지 않은 항목은 원문의 `unknown`, 관찰 또는 추정 상태를 유지했고, 수치 불일치와 오타도 한국어 해설에서 명시해 근거 없이 교정하지 않았습니다.