x86 APIC·IOAPIC·MSI: vector에서 Linux IRQ까지

1345	if (!lapic_is_integrated())		/* 82489DX */
1346		value |= APIC_LVT_LEVEL_TRIGGER;
1347	if (apic_extnmi == APIC_EXTNMI_NONE)
1348		value |= APIC_LVT_MASKED;
1349	apic_write(APIC_LVT1, value);
1350}
1351 
1352static void __init apic_bsp_setup(bool upmode);
1353 
1354/* Init the interrupt delivery mode for the BSP */
1355void __init apic_intr_mode_init(void)
1356{
1357	bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1358 
1359	switch (apic_intr_mode) {
1360	case APIC_PIC:
1361		pr_info("APIC: Keep in PIC mode(8259)\n");
1362		return;
1363	case APIC_VIRTUAL_WIRE:
1364		pr_info("APIC: Switch to virtual wire mode setup\n");
1365		break;
1366	case APIC_VIRTUAL_WIRE_NO_CONFIG:
1367		pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1368		upmode = true;
1369		break;
1370	case APIC_SYMMETRIC_IO:
1371		pr_info("APIC: Switch to symmetric I/O mode setup\n");
1372		break;
1373	case APIC_SYMMETRIC_IO_NO_ROUTING:
1374		pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1375		break;
1376	}
1377 
1378	x86_64_probe_apic();
1379 
1380	if (x86_platform.apic_post_init)
1381		x86_platform.apic_post_init();
1382 
1383	apic_bsp_setup(upmode);
1384}
1385 
1386static void lapic_setup_esr(void)
1387{
1388	unsigned int oldvalue, value, maxlvt;
1389 
1390	if (!lapic_is_integrated()) {
1391		pr_info("No ESR for 82489DX.\n");
1392		return;
1393	}
1394 
1395	if (apic->disable_esr) {
1396		/*
1397		 * Something untraceable is creating bad interrupts on
1398		 * secondary quads ... for the moment, just leave the
1399		 * ESR disabled - we can't do anything useful with the
1400		 * errors anyway - mbligh
1401		 */
1402		pr_info("Leaving ESR disabled.\n");
1403		return;
1404	}
1405 
1406	maxlvt = lapic_get_maxlvt();
1407	if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
1408		apic_write(APIC_ESR, 0);
1409	oldvalue = apic_read(APIC_ESR);
1410 
1411	/* enables sending errors */
1412	value = ERROR_APIC_VECTOR;
1413	apic_write(APIC_LVTERR, value);

310	handle_irq(desc, regs);
311	return true;
312}
313 
314/*
315 * common_interrupt() handles all normal device IRQ's (the special SMP
316 * cross-CPU interrupts have their own entry points).
317 */
318DEFINE_IDTENTRY_IRQ(common_interrupt)
319{
320	struct pt_regs *old_regs = set_irq_regs(regs);
321 
322	/* entry code tells RCU that we're not quiescent.  Check it. */
323	RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
324 
325	if (unlikely(!call_irq_handler(vector, regs)))
326		apic_eoi();
327 
328	set_irq_regs(old_regs);
329}
330 
331#ifdef CONFIG_X86_LOCAL_APIC
332/* Function pointer for generic interrupt vector handling */
333void (*x86_platform_ipi_callback)(void) = NULL;
334/*
335 * Handler for X86_PLATFORM_IPI_VECTOR.
336 */
337DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi)
338{
339	struct pt_regs *old_regs = set_irq_regs(regs);
340 
341	apic_eoi();
342	trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
343	inc_irq_stat(x86_platform_ipis);
344	if (x86_platform_ipi_callback)
345		x86_platform_ipi_callback();
346	trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
347	set_irq_regs(old_regs);
348}
349#endif
350 
351#if IS_ENABLED(CONFIG_KVM)
352static void dummy_handler(void) {}
353static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
354 
355void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
356{