MPIC interrupt controller | Linux 6.18.37

요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.

1. 요약·해설

원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.

요약·해설

mpic.rst:1-58

Freescale MPIC v2.0·v4.2의 MMIO, register, IRQ input과 irqchip routing ABI입니다.

2. 영어 원문 전체

번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.

원문 전체 펼치기

1 .. SPDX-License-Identifier: GPL-2.0

3 =========================

4 MPIC interrupt controller

5 =========================

7 Device types supported:

9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0

10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2

12 Only one MPIC instance, of any type, may be instantiated. The created

13 MPIC will act as the system interrupt controller, connecting to each

14 vcpu's interrupt inputs.

16 Groups:

17 KVM_DEV_MPIC_GRP_MISC

18 Attributes:

20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)

21 Base address of the 256 KiB MPIC register space. Must be

22 naturally aligned. A value of zero disables the mapping.

23 Reset value is zero.

25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)

26 Access an MPIC register, as if the access were made from the guest.

27 "attr" is the byte offset into the MPIC register space. Accesses

28 must be 4-byte aligned.

30 MSIs may be signaled by using this attribute group to write

31 to the relevant MSIIR.

33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)

34 IRQ input line for each standard openpic source. 0 is inactive and 1

35 is active, regardless of interrupt sense.

37 For edge-triggered interrupts: Writing 1 is considered an activating

38 edge, and writing 0 is ignored. Reading returns 1 if a previously

39 signaled edge has not been acknowledged, and 0 otherwise.

41 "attr" is the IRQ number. IRQ numbers for standard sources are the

42 byte offset of the relevant IVPR from EIVPR0, divided by 32.

44 IRQ Routing:

46 The MPIC emulation supports IRQ routing. Only a single MPIC device can

47 be instantiated. Once that device has been created, it's available as

48 irqchip id 0.

50 This irqchip 0 has 256 interrupt pins, which expose the interrupts in

51 the main array of interrupt sources (a.k.a. "SRC" interrupts).

53 The numbering is the same as the MPIC device tree binding -- based on

54 the register offset from the beginning of the sources array, without

55 regard to any subdivisions in chip documentation such as "internal"

56 or "external" interrupts.

58 Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.

3. 한국어 전문 번역

영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.

MPIC device와 attribute group

1-43

KVM은 `KVM_DEV_TYPE_FSL_MPIC_20` Freescale MPIC v2.0과 `KVM_DEV_TYPE_FSL_MPIC_42` v4.2를 지원합니다. Type과 관계없이 VM에는 MPIC 하나만 만들 수 있고 system interrupt controller로서 각 vCPU interrupt input에 연결됩니다.

MPIC attribute group

Group·attribute계약

`KVM_DEV_MPIC_GRP_MISC / KVM_DEV_MPIC_BASE_ADDR`256KiB MPIC register space의 naturally aligned 64-bit base. 0은 mapping disable이며 reset 값도 0

`KVM_DEV_MPIC_GRP_REGISTER`Guest access와 같은 32-bit register read/write. `attr`은 4-byte aligned register-space byte offset

`KVM_DEV_MPIC_GRP_IRQ_ACTIVE`Standard OpenPIC source별 32-bit input line. `attr`은 IRQ number, 값 0 inactive·1 active

MMIO mapping, guest-style register access와 input-line 상태를 제어합니다.

MSI는 REGISTER group으로 해당 MSIIR에 write해 signal할 수 있습니다. Standard-source IRQ number는 `EIVPR0`에서 해당 IVPR까지 byte offset을 32로 나눈 값입니다.

Edge-triggered interrupt에 1을 쓰면 activating edge이고 0 write는 무시됩니다. Read는 이전에 signal한 edge가 아직 acknowledge되지 않았으면 1, 그 밖에는 0을 반환합니다. 이 input value는 configured interrupt sense와 무관합니다.

.. SPDX-License-Identifier: GPL-2.0

=========================
MPIC interrupt controller
=========================

Device types supported:

  - KVM_DEV_TYPE_FSL_MPIC_20     Freescale MPIC v2.0
  - KVM_DEV_TYPE_FSL_MPIC_42     Freescale MPIC v4.2

Only one MPIC instance, of any type, may be instantiated.  The created
MPIC will act as the system interrupt controller, connecting to each
vcpu's interrupt inputs.

Groups:
  KVM_DEV_MPIC_GRP_MISC
   Attributes:

    KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
      Base address of the 256 KiB MPIC register space.  Must be
      naturally aligned.  A value of zero disables the mapping.
      Reset value is zero.

  KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
    Access an MPIC register, as if the access were made from the guest.
    "attr" is the byte offset into the MPIC register space.  Accesses
    must be 4-byte aligned.

    MSIs may be signaled by using this attribute group to write
    to the relevant MSIIR.

  KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
    IRQ input line for each standard openpic source.  0 is inactive and 1
    is active, regardless of interrupt sense.

    For edge-triggered interrupts:  Writing 1 is considered an activating
    edge, and writing 0 is ignored.  Reading returns 1 if a previously
    signaled edge has not been acknowledged, and 0 otherwise.

    "attr" is the IRQ number.  IRQ numbers for standard sources are the
    byte offset of the relevant IVPR from EIVPR0, divided by 32.

MPIC IRQ routing

44-58

MPIC emulation은 IRQ routing을 지원합니다. 유일한 MPIC device를 만든 뒤 irqchip ID 0으로 사용할 수 있습니다.

Irqchip 0은 main source array의 SRC interrupt를 노출하는 256개 pin을 가집니다. Numbering은 MPIC device-tree binding과 동일하게 source array 시작점부터 register offset을 사용하며 chip 문서의 internal·external subdivision은 고려하지 않습니다.

SRC가 아닌 interrupt는 IRQ routing mechanism을 통해 access할 수 없습니다.

IRQ Routing:

  The MPIC emulation supports IRQ routing. Only a single MPIC device can
  be instantiated. Once that device has been created, it's available as
  irqchip id 0.

  This irqchip 0 has 256 interrupt pins, which expose the interrupts in
  the main array of interrupt sources (a.k.a. "SRC" interrupts).

  The numbering is the same as the MPIC device tree binding -- based on
  the register offset from the beginning of the sources array, without
  regard to any subdivisions in chip documentation such as "internal"
  or "external" interrupts.

  Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.