요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
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.. SPDX-License-Identifier: GPL-2.0
3
===============================================
4
PPE Ethernet Driver for Qualcomm IPQ SoC Family
5
===============================================
7
Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
9
Author: Lei Wei <quic_leiwei@quicinc.com>
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Contents
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========
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- `PPE Overview`_
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- `PPE Driver Overview`_
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- `PPE Driver Supported SoCs`_
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- `Enabling the Driver`_
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- `Debugging`_
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PPE Overview
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============
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IPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcomm's series of
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networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet
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packet process engine in the IPQ SoC.
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Below is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and
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other blocks which are in the SoC but outside the PPE engine. These blocks work together
31
to enable the Ethernet for the IPQ SoC::
33
+------+ +------+ +------+ +------+ +------+ +------+ start +-------+
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|netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK|
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+------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+
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| | | ^
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+-------+ +-------------------------+--------+----------------------+ | | |
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| GCC | | | EDMA | | | | |
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+---+---+ | PPE +---+----+ | | | |
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| clk | | | | | |
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+-------->| +-----------------------+------+-----+---------------+ | | | |
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| | Switch Core |Port0 | |Port7(EIP FIFO)| | | | |
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| | +---+--+ +------+--------+ | | | |
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| | | | | | | | |
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+-------+ | | +------+---------------+----+ | | | | |
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|CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | |
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+---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | |
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| | | | +---+ +---+ +----+ | +--------+ | | | | | |
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| | | | +------+--------------------+ | | | | |
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| | | | | | | | | |
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| v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | |
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| +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | |
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| |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | |
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| +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | |
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| ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | |
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| | | +------>| +----|------|-------|-------|---------|--------|-----+ | | |
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| | | +---------------------------------------------------------+ | |
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| | | | | | | | | | |
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| | | MII clk | QSGMII USXGMII USXGMII | |
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| | +--------------->| | | | | | | |
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| | +-------------------------+ +---------+ +---------+ | |
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| |125/312.5MHz clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | |
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| +----------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ |
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+----------------->| | | | | | |
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| 31.25MHz ref clk +-------------------------+ +---------+ +---------+ |
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| | | | | | | |
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| +-----------------------------------------------------+ |
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|25/50MHz ref clk| +-------------------------+ +------+ +------+ | link |
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+--------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+
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| +-------------------------+ +------+ +------+ | change
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| |
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| MDIO bus |
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+-----------------------------------------------------+
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The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global
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Clock Controller) blocks are in the SoC and act as clock providers.
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The UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and
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XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface
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modes between the PPE MAC and the external PHY.
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This documentation focuses on the descriptions of PPE engine and the PPE driver.
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The Ethernet functionality in the PPE (Packet Process Engine) is comprised of three
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components: the switch core, port wrapper and Ethernet DMA.
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The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO
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interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU
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communication using Ethernet DMA. The other one is used to communicate to the EIP
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engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs
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that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer
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Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the
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packet processing.
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The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting
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various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS)
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instances supported on the IPQ9574.
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Ethernet DMA is used to transmit and receive packets between the Ethernet subsystem
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and ARM host CPU.
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The following lists the main blocks in the PPE engine which will be driven by this
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PPE driver:
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- BM
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BM is the hardware buffer manager for the PPE switch ports.
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- QM
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Queue Manager for managing the egress hardware queues of the PPE switch ports.
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- SCH
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The scheduler which manages the hardware traffic scheduling for the PPE switch ports.
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- L2
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The L2 block performs the packet bridging in the switch core. The bridge domain is
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represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be
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enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.
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- MAC
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The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding
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to six switch ports (port1 to port6). The MAC block is connected with external PHY
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through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and
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the switch port can select to use GMAC or XMAC through a MUX selection according to
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the external PHY's capability.
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- EDMA (Ethernet DMA)
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The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE
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ports and the ARM cores.
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The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can
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be also forwarded to internal switch port0 so that the packet can be delivered to the
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ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the
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packet to the corresponding 'netdevice' interface.
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The software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact
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with the Linux PHYLINK framework to manage the connectivity between the PPE ports and
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the connected PHYs, and the port link states. This is also illustrated in above diagram.
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PPE Driver Overview
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===================
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PPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver
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which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the
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various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part
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drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables
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the netdevice driver for the PPE ports.
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The PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below:
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- Makefile
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- ppe.c
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- ppe.h
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- ppe_config.c
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- ppe_config.h
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- ppe_debugfs.c
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- ppe_debugfs.h
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- ppe_regs.h
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The ppe.c file contains the main PPE platform driver and undertakes the initialization of
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PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware
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blocks are provided in the ppe_config.c file.
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The ppe.h defines the PPE device data structure which will be used by PPE driver functions.
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The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters,
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CPU code counters and queue counters.
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PPE Driver Supported SoCs
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=========================
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The PPE driver supports the following IPQ SoC:
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- IPQ9574
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Enabling the Driver
173
===================
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The driver is located in the menu structure at::
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-> Device Drivers
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-> Network device support (NETDEVICES [=y])
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-> Ethernet driver support
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-> Qualcomm devices
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-> Qualcomm Technologies, Inc. PPE Ethernet support
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If the driver is built as a module, the module will be called qcom-ppe.
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The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers.
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Please make sure the dependent modules are installed before installing the PPE driver
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module.
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Debugging
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=========
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The PPE hardware counters can be accessed using debugfs interface from the
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``/sys/kernel/debug/ppe/`` directory.
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
Qualcomm IPQ PPE Ethernet 드라이버 소개
1-21이 문서는 `GPL-2.0` 라이선스를 따릅니다.
Qualcomm IPQ SoC 제품군용 PPE Ethernet 드라이버
Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
작성자: Lei Wei <quic_leiwei@quicinc.com>
목차
- PPE 개요
- PPE 드라이버 개요
- PPE 드라이버가 지원하는 SoC
- 드라이버 활성화
- 디버깅
.. SPDX-License-Identifier: GPL-2.0
===============================================
PPE Ethernet Driver for Qualcomm IPQ SoC Family
===============================================
Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
Author: Lei Wei <quic_leiwei@quicinc.com>
Contents
========
- `PPE Overview`_
- `PPE Driver Overview`_
- `PPE Driver Supported SoCs`_
- `Enabling the Driver`_
- `Debugging`_
IPQ9574 PPE 하드웨어 구조
22-100PPE 개요
IPQ(Qualcomm Internet Processor) SoC(System-on-Chip) 계열은 Wi-Fi 액세스 포인트를 위한 Qualcomm 네트워킹 SoC 제품군입니다. PPE(Packet Process Engine)는 IPQ SoC 안의 Ethernet 패킷 처리 엔진입니다.
원문의 IPQ9574 단순화 하드웨어 도식은 PPE 엔진과 SoC 안에서 PPE 밖에 있는 블록을 함께 보여 줍니다. 이 블록들이 협력해 IPQ SoC의 Ethernet 기능을 구성합니다.
외부 PHY→UNIPHY PCS/XPCS→MAC0~MAC5 / Port1~Port6→PPE Switch Core→Port0→EDMA→ARM CPU / netdev
PPE Switch Core→Port7 EIP FIFO→EIP IPsec offload
외부 PHY에서 ARM 호스트와 IPsec 엔진으로 이어지는 주요 경로를 구조화했습니다.
CMN PLL→NSSCC→UNIPHY와 MII/ref clock
GCC→PPE clock
netdev→PHYLINK→MAC/PCS ops→외부 PHY link state
MDIO bus→외부 PHY 구성
PHYLINK와 SoC 클록 공급자가 데이터 경로를 보조합니다.
CMN(Common) PLL, NSSCC(Networking Sub System Clock Controller), GCC(Global Clock Controller)는 SoC 안에서 클록 공급자 역할을 합니다.
UNIPHY 블록도 SoC 내부에 있으며 PPE MAC과 외부 PHY 사이의 여러 인터페이스 모드를 지원하도록 PCS(Physical Coding Sublayer)와 XPCS(10-Gigabit Physical Coding Sublayer) 기능을 제공합니다.
이 문서는 PPE 엔진과 PPE 드라이버 설명에 초점을 둡니다.
PPE의 Ethernet 기능은 스위치 코어, 포트 래퍼, Ethernet DMA의 세 구성 요소로 이루어집니다.
IPQ9574 PPE의 스위치 코어에는 최대 6개의 전면 패널 포트와 두 FIFO 인터페이스가 있습니다. 첫 번째 FIFO는 Ethernet DMA를 통해 Ethernet 포트와 호스트 CPU가 통신하는 데 쓰입니다. 두 번째 FIFO는 IPsec 오프로딩용 EIP 엔진과 통신합니다. PPE는 외부 Ethernet PHY에 연결할 수 있는 GMAC/XGMAC 6개를 포함합니다. 스위치 코어에는 패킷 처리를 지원하는 BM(Buffer Management), QM(Queue Management), SCH(Scheduler) 모듈도 있습니다.
포트 래퍼는 6개의 GMAC/XGMAC을 UNIPHY(PCS)에 연결하며 SGMII, QSGMII, PSGMII, USXGMII, 10G-BASER 같은 모드를 지원합니다. IPQ9574는 UNIPHY(PCS) 인스턴스 3개를 지원합니다.
Ethernet DMA는 Ethernet 서브시스템과 ARM 호스트 CPU 사이에서 패킷을 송수신하는 데 사용됩니다.
PPE Overview
============
IPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcomm's series of
networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet
packet process engine in the IPQ SoC.
Below is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and
other blocks which are in the SoC but outside the PPE engine. These blocks work together
to enable the Ethernet for the IPQ SoC::
+------+ +------+ +------+ +------+ +------+ +------+ start +-------+
|netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK|
+------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+
| | | ^
+-------+ +-------------------------+--------+----------------------+ | | |
| GCC | | | EDMA | | | | |
+---+---+ | PPE +---+----+ | | | |
| clk | | | | | |
+-------->| +-----------------------+------+-----+---------------+ | | | |
| | Switch Core |Port0 | |Port7(EIP FIFO)| | | | |
| | +---+--+ +------+--------+ | | | |
| | | | | | | | |
+-------+ | | +------+---------------+----+ | | | | |
|CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | |
+---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | |
| | | | +---+ +---+ +----+ | +--------+ | | | | | |
| | | | +------+--------------------+ | | | | |
| | | | | | | | | |
| v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | |
| +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | |
| |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | |
| +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | |
| ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | |
| | | +------>| +----|------|-------|-------|---------|--------|-----+ | | |
| | | +---------------------------------------------------------+ | |
| | | | | | | | | | |
| | | MII clk | QSGMII USXGMII USXGMII | |
| | +--------------->| | | | | | | |
| | +-------------------------+ +---------+ +---------+ | |
| |125/312.5MHz clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | |
| +----------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ |
+----------------->| | | | | | |
| 31.25MHz ref clk +-------------------------+ +---------+ +---------+ |
| | | | | | | |
| +-----------------------------------------------------+ |
|25/50MHz ref clk| +-------------------------+ +------+ +------+ | link |
+--------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+
| +-------------------------+ +------+ +------+ | change
| |
| MDIO bus |
+-----------------------------------------------------+
The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global
Clock Controller) blocks are in the SoC and act as clock providers.
The UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and
XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface
modes between the PPE MAC and the external PHY.
This documentation focuses on the descriptions of PPE engine and the PPE driver.
The Ethernet functionality in the PPE (Packet Process Engine) is comprised of three
components: the switch core, port wrapper and Ethernet DMA.
The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO
interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU
communication using Ethernet DMA. The other one is used to communicate to the EIP
engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs
that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer
Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the
packet processing.
The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting
various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS)
instances supported on the IPQ9574.
Ethernet DMA is used to transmit and receive packets between the Ethernet subsystem
and ARM host CPU.PPE 블록과 패킷 전달 경로
101-134PPE 드라이버가 구동하는 주요 PPE 엔진 블록은 다음과 같습니다.
블록역할
BMPPE 스위치 포트용 하드웨어 버퍼 관리자
QMPPE 스위치 포트의 송신 하드웨어 큐 관리자
SCHPPE 스위치 포트의 하드웨어 트래픽 스케줄러
L2VSI 도메인 안에서 FDB 학습과 브리지 전달 수행
MACPort1~Port6에 대응하는 MAC0~MAC5; PHY 성능에 따라 GMAC/XGMAC 선택
EDMAPPE 포트와 ARM 코어 사이의 Ethernet 패킷 송수신
스위치 코어와 호스트 패킷 경로를 구성하는 블록입니다.
L2 블록은 스위치 코어에서 패킷 브리징을 수행합니다. 브리지 도메인은 PPE에서 VSI(Virtual Switch Instance) 도메인으로 표현됩니다. VSI 도메인을 기준으로 FDB 학습을 활성화할 수 있고, 브리지 전달도 VSI 도메인 안에서 이루어집니다.
IPQ9574 PPE는 스위치 포트 1~6에 대응하는 MAC0~MAC5, 즉 최대 6개의 MAC을 지원합니다. 각 MAC은 UNIPHY PCS를 통해 외부 PHY에 연결됩니다. MAC 블록은 GMAC과 XGMAC을 포함하며, 스위치 포트는 외부 PHY의 기능에 따라 MUX로 GMAC 또는 XMAC을 선택합니다.
PPE MAC 포트에서 받은 패킷은 다른 PPE MAC 포트로 전달할 수 있습니다. 내부 스위치 Port0로 전달한 뒤 EDMA 엔진을 이용해 ARM 코어로 보낼 수도 있습니다. EDMA 드라이버는 패킷을 해당 `netdevice` 인터페이스에 전달합니다.
PPE MAC의 소프트웨어 인스턴스인 netdevice, PCS, 외부 PHY는 Linux PHYLINK 프레임워크와 상호작용하여 PPE 포트와 PHY 사이의 연결 및 포트 링크 상태를 관리합니다.
The following lists the main blocks in the PPE engine which will be driven by this
PPE driver:
- BM
BM is the hardware buffer manager for the PPE switch ports.
- QM
Queue Manager for managing the egress hardware queues of the PPE switch ports.
- SCH
The scheduler which manages the hardware traffic scheduling for the PPE switch ports.
- L2
The L2 block performs the packet bridging in the switch core. The bridge domain is
represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be
enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.
- MAC
The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding
to six switch ports (port1 to port6). The MAC block is connected with external PHY
through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and
the switch port can select to use GMAC or XMAC through a MUX selection according to
the external PHY's capability.
- EDMA (Ethernet DMA)
The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE
ports and the ARM cores.
The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can
be also forwarded to internal switch port0 so that the packet can be delivered to the
ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the
packet to the corresponding 'netdevice' interface.
The software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact
with the Linux PHYLINK framework to manage the connectivity between the PPE ports and
the connected PHYs, and the port link states. This is also illustrated in above diagram.
드라이버 구성, 활성화와 디버깅
135-194PPE 드라이버 개요
PPE 드라이버는 Qualcomm IPQ SoC용 Ethernet 드라이버입니다. PPE 부분과 Ethernet DMA 부분을 하나의 platform driver로 구현합니다. PPE 부분은 BM, QM, L2, PPE MAC 등 PPE 스위치 코어의 여러 블록을 초기화하고 구동합니다. EDMA 부분은 PPE 포트와 ARM 코어 사이의 패킷 전송을 위한 Ethernet DMA를 구동하고 PPE 포트용 netdevice 드라이버를 활성화합니다.
`drivers/net/ethernet/qualcomm/ppe/`의 PPE 드라이버 파일은 다음과 같습니다.
- Makefile
- ppe.c
- ppe.h
- ppe_config.c
- ppe_config.h
- ppe_debugfs.c
- ppe_debugfs.h
- ppe_regs.h`ppe.c`에는 주 PPE platform driver가 있으며 QM, BM, L2 같은 PPE 스위치 코어 블록을 초기화합니다. 이 하드웨어 블록의 구성 API는 `ppe_config.c`에 있습니다.
`ppe.h`는 PPE 드라이버 함수가 사용하는 PPE 장치 데이터 구조를 정의합니다.
`ppe_debugfs.c`는 PPE 포트 RX/TX, CPU 코드, 큐 카운터 같은 PPE 통계 카운터를 제공합니다.
PPE 드라이버가 지원하는 SoC
현재 지원하는 IPQ SoC는 `IPQ9574`입니다.
드라이버 활성화
메뉴에서 드라이버는 다음 위치에 있습니다.
Device Drivers
Network device support (NETDEVICES [=y])
Ethernet driver support
Qualcomm devices
Qualcomm Technologies, Inc. PPE Ethernet support모듈로 빌드하면 이름은 `qcom-ppe`입니다. PPE 드라이버는 기능상 CMN PLL과 NSSCC 클록 컨트롤러 드라이버에 의존합니다. PPE 드라이버 모듈을 설치하기 전에 의존 모듈이 설치되어 있는지 확인하십시오.
디버깅
PPE 하드웨어 카운터는 debugfs의 `/sys/kernel/debug/ppe/` 디렉터리에서 확인할 수 있습니다.
PPE Driver Overview
===================
PPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver
which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the
various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part
drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables
the netdevice driver for the PPE ports.
The PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below:
- Makefile
- ppe.c
- ppe.h
- ppe_config.c
- ppe_config.h
- ppe_debugfs.c
- ppe_debugfs.h
- ppe_regs.h
The ppe.c file contains the main PPE platform driver and undertakes the initialization of
PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware
blocks are provided in the ppe_config.c file.
The ppe.h defines the PPE device data structure which will be used by PPE driver functions.
The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters,
CPU code counters and queue counters.
PPE Driver Supported SoCs
=========================
The PPE driver supports the following IPQ SoC:
- IPQ9574
Enabling the Driver
===================
The driver is located in the menu structure at::
-> Device Drivers
-> Network device support (NETDEVICES [=y])
-> Ethernet driver support
-> Qualcomm devices
-> Qualcomm Technologies, Inc. PPE Ethernet support
If the driver is built as a module, the module will be called qcom-ppe.
The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers.
Please make sure the dependent modules are installed before installing the PPE driver
module.
Debugging
=========
The PPE hardware counters can be accessed using debugfs interface from the
``/sys/kernel/debug/ppe/`` directory.
요약·해설
ppe.rst:1-194PPE 드라이버는 IPQ9574의 내장 Ethernet 스위치와 호스트 DMA 경로를 하나의 platform driver로 관리합니다. 외부 PHY 트래픽은 UNIPHY와 MAC을 거쳐 스위치 코어에 들어오며, 호스트로 향하는 패킷은 Port0과 EDMA를 통해 ARM netdevice에 전달됩니다.
브리지 전달, 호스트 전달, IPsec 오프로딩 경로를 나눠 볼 수 있습니다.
주요 소스 파일과 역할입니다.