Xilinx ZynqMP UltraScale+ DisplayPort

ZynqMP DisplayPort subsystem 개요

이 subsystem은 Xilinx ZynqMP UltraScale+에서 DisplayPort video와 audio output을 처리합니다.

DisplayPort DMA controller인 `xilinx-dpdma`가 in-memory framebuffer를 공급하는 방식과 programmable logic(PL)에서 live video·audio를 받는 방식을 모두 지원합니다.

Subsystem은 color-space conversion, alpha blending, audio mixing 등의 transformation을 수행할 수 있지만 현재 모든 기능이 지원되는 것은 아닙니다.

.. SPDX-License-Identifier: GPL-2.0+

===============================================
Xilinx ZynqMP Ultrascale+ DisplayPort Subsystem
===============================================

This subsystem handles DisplayPort video and audio output on the ZynqMP. It
supports in-memory framebuffers with the DisplayPort DMA controller
(xilinx-dpdma), as well as "live" video and audio from the programmable logic
(PL). This subsystem can perform several transformations, including color space
conversion, alpha blending, and audio mixing, although not all features are
currently supported.

DisplayPort debugfs 시험 모드

Debugging과 compliance test를 위해 `/sys/kernel/debug/dri/X/DP-1/test/` 아래의 여러 debugfs file로 DisplayPort test mode를 제어합니다.

`active`에 1을 쓰면 test mode가 활성화되고 0을 쓰면 비활성화됩니다. 이미 같은 상태여도 다시 활성화·비활성화 동작을 수행합니다. Inactive일 때 다른 file 변경은 즉시 적용되지 않지만 저장됐다가 활성화 시 반영되고, active일 때는 즉시 적용됩니다.

`custom`은 custom test pattern 값입니다. `downspread`는 1/0으로 spread-spectrum clocking을 켜거나 끄고, `enhanced`는 enhanced framing을 제어합니다.

`ignore_aux_errors=1`은 AUX error를 무시합니다. 이 file은 test mode 상태와 관계없이 즉시 적용되고 모든 AUX transfer에 영향을 줍니다. `ignore_hpd=1`은 cable 제거 또는 monitor link retraining request 같은 hotplug event를 무시하며 역시 즉시 적용됩니다.

`laneX_preemphasis`는 lane X의 pre-emphasis를 0(최저)부터 2(최고)까지 설정합니다. `laneX_swing`은 voltage swing을 0부터 3까지 설정합니다. `lanes`는 사용할 lane 수를 1, 2, 4 중에서 고릅니다.

`pattern`은 `video`, symbol-error measurement용 `symbol-error`, 다항식 `x^7 + x^6 + 1`의 `prbs7`, custom 80-bit pattern인 `80bit-custom`, HBR2 compliance eye pattern인 `cp2520`, link-training symbol `tps1`(`/D10.2/`), `tps2`, HBR2용 `tps3` 중 하나입니다.

`rate`는 hertz 단위이며 `5400000000`(HBR2), `2700000000`(HBR), `1620000000`(RBR) 중 하나입니다.

모든 설정은 아래 shell loop로 dump할 수 있습니다. `custom`은 `hexdump -C`로 첫 줄을 보고 나머지는 `cat`으로 읽습니다.

for prop in /sys/kernel/debug/dri/1/DP-1/test/*; do
        printf '%-17s ' ${prop##*/}
        if [ ${prop##*/} = custom ]; then
                hexdump -C $prop | head -1
        else
                cat $prop
        fi
done

예시 출력은 active 1, enhanced 1, AUX·HPD 무시 1, lane 0·1의 pre-emphasis 0과 swing 3, 2 lanes, `prbs7`, RBR `1620000000`을 보여 줍니다.

권장 절차는 board를 monitor에 연결하고 test mode를 구성·활성화한 다음 cable을 빼서 원하는 test equipment에 연결하는 것입니다. 아래 예시는 enhanced framing, TPS1, RBR, AUX error·HPD 무시를 설정하고 test mode를 활성화합니다.

echo 1 > /sys/kernel/debug/dri/1/DP-1/test/enhanced
echo tps1 > /sys/kernel/debug/dri/1/DP-1/test/pattern
echo 1620000000 > /sys/kernel/debug/dri/1/DP-1/test/rate
echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_aux_errors
echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_hpd
echo 1 > /sys/kernel/debug/dri/1/DP-1/test/active

debugfs
-------

To support debugging and compliance testing, several test modes can be enabled
though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/
control the DisplayPort test modes:

active:
        Writing a 1 to this file will activate test mode, and writing a 0 will
        deactivate test mode. Writing a 1 or 0 when the test mode is already
        active/inactive will re-activate/re-deactivate test mode. When test
        mode is inactive, changes made to other files will have no (immediate)
        effect, although the settings will be saved for when test mode is
        activated. When test mode is active, changes made to other files will
        apply immediately.

custom:
        Custom test pattern value

downspread:
        Enable/disable clock downspreading (spread-spectrum clocking) by
        writing 1/0

enhanced:
        Enable/disable enhanced framing

ignore_aux_errors:
        Ignore AUX errors when set to 1. Writes to this file take effect
        immediately (regardless of whether test mode is active) and affect all
        AUX transfers.

ignore_hpd:
        Ignore hotplug events (such as cable removals or monitor link
        retraining requests) when set to 1. Writes to this file take effect
        immediately (regardless of whether test mode is active).

laneX_preemphasis:
        Preemphasis from 0 (lowest) to 2 (highest) for lane X

laneX_swing:
        Voltage swing from 0 (lowest) to 3 (highest) for lane X

lanes:
        Number of lanes to use (1, 2, or 4)

pattern:
        Test pattern. May be one of:

                video
                        Use regular video input

                symbol-error
                        Symbol error measurement pattern

                prbs7
                        Output of the PRBS7 (x^7 + x^6 + 1) polynomial

                80bit-custom
                        A custom 80-bit pattern

                cp2520
                        HBR2 compliance eye pattern

                tps1
                        Link training symbol pattern TPS1 (/D10.2/)

                tps2
                        Link training symbol pattern TPS2

                tps3
                        Link training symbol pattern TPS3 (for HBR2)

rate:
        Rate in hertz. One of

                * 5400000000 (HBR2)
                * 2700000000 (HBR)
                * 1620000000 (RBR)

You can dump the displayport test settings with the following command::

        for prop in /sys/kernel/debug/dri/1/DP-1/test/*; do
                printf '%-17s ' ${prop##*/}
                if [ ${prop##*/} = custom ]; then
                        hexdump -C $prop | head -1
                else
                        cat $prop
                fi
        done

The output could look something like::

        active            1
        custom            00000000  00 00 00 00 00 00 00 00  00 00                    |..........|
        downspread        0
        enhanced          1
        ignore_aux_errors 1
        ignore_hpd        1
        lane0_preemphasis 0
        lane0_swing       3
        lane1_preemphasis 0
        lane1_swing       3
        lanes             2
        pattern           prbs7
        rate              1620000000

The recommended test procedure is to connect the board to a monitor,
configure test mode, activate test mode, and then disconnect the cable
and connect it to your test equipment of choice. For example, one
sequence of commands could be::

        echo 1 > /sys/kernel/debug/dri/1/DP-1/test/enhanced
        echo tps1 > /sys/kernel/debug/dri/1/DP-1/test/pattern
        echo 1620000000 > /sys/kernel/debug/dri/1/DP-1/test/rate
        echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_aux_errors
        echo 1 > /sys/kernel/debug/dri/1/DP-1/test/ignore_hpd
        echo 1 > /sys/kernel/debug/dri/1/DP-1/test/active

at which point the cable could be disconnected from the monitor.

ZynqMP DisplayPort 내부 API

내부 API 문서는 세 header와 세 implementation source의 kernel-doc를 포함합니다.

Header는 `drivers/gpu/drm/xlnx/zynqmp_disp.h`, `zynqmp_dpsub.h`, `zynqmp_kms.h`이며 display, DisplayPort subsystem, KMS object의 interface를 정의합니다.

Implementation은 `zynqmp_disp.c`, `zynqmp_dp.c`, `zynqmp_kms.c`이며 display pipeline, DisplayPort link와 DRM KMS 통합을 구현합니다.

Internals
---------

.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_disp.h

.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_dpsub.h

.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_kms.h

.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_disp.c

.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_dp.c

.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_kms.c