PINCTRL subsystem

pinctrl 서브시스템과 최상위 pin controller 인터페이스

pinctrl 서브시스템은 SoC의 pin, pin group, pin function을 열거하고 이름을 붙이며, pad 또는 finger의 multiplexing을 제어하고, pull-up·pull-down·open drain·load capacitance 같은 전기적 pin configuration을 다룹니다. 이 문서에서 PIN CONTROLLER는 pin을 제어하는 하드웨어 블록 하나를 뜻하며, 각 controller는 서로 독립된 local pin number space를 가집니다.

8x8 PGA 예에서는 A1부터 H8까지 64개 물리 pin이 있지만, 드라이버가 반드시 연속된 0..63 번호를 만들 필요는 없습니다. `struct pinctrl_pin_desc` 배열에서 `PINCTRL_PIN(number, name)`으로 하드웨어에 자연스러운 sparse 번호와 사람이 읽을 수 있는 이름을 선언합니다. 번호는 가능하면 register offset, datasheet pin 번호, GPIO line 범위와 맞추어 디버깅과 교차 참조를 쉽게 해야 합니다.

controller 드라이버는 `struct pinctrl_desc`에 pin 배열, pin 수, `pinctrl_ops`, `pinmux_ops`, `pinconf_ops`, 소유 모듈을 채운 뒤 `pinctrl_register_and_init()`을 호출합니다. 이 함수가 성공한 뒤에만 필요한 초기화를 수행하고, 마지막으로 `pinctrl_enable()`을 호출해 controller를 사용할 수 있게 합니다. Kconfig에서는 해당 architecture 또는 SoC가 pin controller를 선택하도록 `select PINCTRL`을 연결할 수 있으며, 실제 예는 `arch/arm/mach-ux500/Kconfig`에서 볼 수 있습니다.

467-pad perimeter 예처럼 pin 수가 많아도 원칙은 같습니다. 물리 패키지의 행·열 또는 외곽 순서를 유지한 이름과 번호를 사용하면 schematic, package drawing, register map 사이를 곧바로 대응시킬 수 있습니다.

===============================
PINCTRL (PIN CONTROL) subsystem
===============================

This document outlines the pin control subsystem in Linux

This subsystem deals with:

- Enumerating and naming controllable pins

- Multiplexing of pins, pads, fingers (etc) see below for details

- Configuration of pins, pads, fingers (etc), such as software-controlled
  biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
  load capacitance etc.

Top-level interface
===================

Definitions:

- A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
  can control PINs. It may be able to multiplex, bias, set load capacitance,
  set drive strength, etc. for individual pins or groups of pins.

- PINS are equal to pads, fingers, balls or whatever packaging input or
  output line you want to control and these are denoted by unsigned integers
  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
  there may be several such number spaces in a system. This pin space may
  be sparse - i.e. there may be gaps in the space with numbers where no
  pin exists.

When a PIN CONTROLLER is instantiated, it will register a descriptor to the
pin control framework, and this descriptor contains an array of pin descriptors
describing the pins handled by this specific pin controller.

Here is an example of a PGA (Pin Grid Array) chip seen from underneath::

        A   B   C   D   E   F   G   H

   8    o   o   o   o   o   o   o   o

   7    o   o   o   o   o   o   o   o

   6    o   o   o   o   o   o   o   o

   5    o   o   o   o   o   o   o   o

   4    o   o   o   o   o   o   o   o

   3    o   o   o   o   o   o   o   o

   2    o   o   o   o   o   o   o   o

   1    o   o   o   o   o   o   o   o

To register a pin controller and name all the pins on this package we can do
this in our driver:

.. code-block:: c

        #include <linux/pinctrl/pinctrl.h>

        const struct pinctrl_pin_desc foo_pins[] = {
                PINCTRL_PIN(0, "A8"),
                PINCTRL_PIN(1, "B8"),
                PINCTRL_PIN(2, "C8"),
                ...
                PINCTRL_PIN(61, "F1"),
                PINCTRL_PIN(62, "G1"),
                PINCTRL_PIN(63, "H1"),
        };

        static struct pinctrl_desc foo_desc = {
                .name = "foo",
                .pins = foo_pins,
                .npins = ARRAY_SIZE(foo_pins),
                .owner = THIS_MODULE,
        };

        int __init foo_init(void)
        {
                int error;

                struct pinctrl_dev *pctl;

                error = pinctrl_register_and_init(&foo_desc, <PARENT>, NULL, &pctl);
                if (error)
                        return error;

                return pinctrl_enable(pctl);
        }

To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
selected drivers, you need to select them from your machine's Kconfig entry,
since these are so tightly integrated with the machines they are used on.
See ``arch/arm/mach-ux500/Kconfig`` for an example.

Pins usually have fancier names than this. You can find these in the datasheet
for your chip. Notice that the core pinctrl.h file provides a fancy macro
called ``PINCTRL_PIN()`` to create the struct entries. As you can see the pins are
enumerated from 0 in the upper left corner to 63 in the lower right corner.
This enumeration was arbitrarily chosen, in practice you need to think
through your numbering system so that it matches the layout of registers
and such things in your driver, or the code may become complicated. You must
also consider matching of offsets to the GPIO ranges that may be handled by
the pin controller.

For a padding with 467 pads, as opposed to actual pins, the enumeration will
be like this, walking around the edge of the chip, which seems to be industry
standard too (all these pads had names, too)::


     0 ..... 104
   466        105
     .        .
     .        .
   358        224
    357 .... 225

pin group 선언과 열거

일부 하드웨어 동작은 pin 하나가 아니라 고정된 pin 집합을 사용합니다. 예를 들어 첫 PGA 배치에서 SPI는 `{ 0, 8, 16, 24 }`, I2C는 `{ 24, 25 }`를 사용하며 pin 24를 공유합니다. 이러한 집합을 pin group으로 선언하면 mux function과 configuration을 일관된 단위로 연결할 수 있습니다.

드라이버는 `struct pinctrl_ops`의 `.get_groups_count()`로 group 수를, `.get_group_name()`으로 각 이름을, `.get_group_pins()`로 group에 속한 pin 번호 배열과 원소 수를 반환합니다. group 이름은 controller 안에서 고유해야 하며, 이후 function-to-group mapping과 debugfs에 그대로 나타나므로 하드웨어 문서와 맞는 안정적인 이름을 사용해야 합니다.

Pin groups
==========

Many controllers need to deal with groups of pins, so the pin controller
subsystem has a mechanism for enumerating groups of pins and retrieving the
actual enumerated pins that are part of a certain group.

For example, say that we have a group of pins dealing with an SPI interface
on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
on { 24, 25 }.

These two groups are presented to the pin control subsystem by implementing
some generic ``pinctrl_ops`` like this:

.. code-block:: c

        #include <linux/pinctrl/pinctrl.h>

        static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
        static const unsigned int i2c0_pins[] = { 24, 25 };

        static const struct pingroup foo_groups[] = {
                PINCTRL_PINGROUP("spi0_grp", spi0_pins, ARRAY_SIZE(spi0_pins)),
                PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
        };

        static int foo_get_groups_count(struct pinctrl_dev *pctldev)
        {
                return ARRAY_SIZE(foo_groups);
        }

        static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
                                              unsigned int selector)
        {
                return foo_groups[selector].name;
        }

        static int foo_get_group_pins(struct pinctrl_dev *pctldev,
                                      unsigned int selector,
                                      const unsigned int **pins,
                                      unsigned int *npins)
        {
                *pins = foo_groups[selector].pins;
                *npins = foo_groups[selector].npins;
                return 0;
        }

        static struct pinctrl_ops foo_pctrl_ops = {
                .get_groups_count = foo_get_groups_count,
                .get_group_name = foo_get_group_name,
                .get_group_pins = foo_get_group_pins,
        };

        static struct pinctrl_desc foo_desc = {
                ...
                .pctlops = &foo_pctrl_ops,
        };

The pin control subsystem will call the ``.get_groups_count()`` function to
determine the total number of legal selectors, then it will call the other functions
to retrieve the name and pins of the group. Maintaining the data structure of
the groups is up to the driver, this is just a simple example - in practice you
may need more entries in your group structure, for example specific register
ranges associated with each group and so on.

pin configuration과 전기적 속성

pin configuration은 mux function 선택과 별개로 pin의 전기적 특성을 설정합니다. 흔한 예로 high impedance 또는 tristate, VDD로 향하는 pull-up resistor, GND로 향하는 pull-down resistor가 있습니다. 하드웨어가 지원하는 drive strength, slew rate, debounce, schmitt trigger 같은 속성도 같은 계층에서 다룹니다.

generic pin configuration 매개변수를 사용할 수 없는 플랫폼 고유 설정은 드라이버 정의 값으로 표현할 수 있습니다. 문서의 `PLATFORM_X_PULL_UP`처럼 해당 controller만 이해하는 config를 만들되, 가능하면 공통 `PIN_CONFIG_*` 의미를 우선 사용해야 다른 드라이버와 consumer가 같은 언어로 상태를 기술할 수 있습니다.

`struct pinconf_ops`는 개별 pin의 `.pin_config_get()`·`.pin_config_set()`과 group 단위의 `.pin_config_group_get()`·`.pin_config_group_set()`을 제공합니다. group operation을 구현하면 동일한 전기 설정을 group 전체에 원자적이거나 효율적으로 적용할 수 있습니다.

Pin configuration
=================

Pins can sometimes be software-configured in various ways, mostly related
to their electronic properties when used as inputs or outputs. For example you
may be able to make an output pin high impedance (Hi-Z), or "tristate" meaning it is
effectively disconnected. You may be able to connect an input pin to VDD or GND
using a certain resistor value - pull up and pull down - so that the pin has a
stable value when nothing is driving the rail it is connected to, or when it's
unconnected.

Pin configuration can be programmed by adding configuration entries into the
mapping table; see section `Board/machine configuration`_ below.

The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
above, is entirely defined by the pin controller driver.

The pin configuration driver implements callbacks for changing pin
configuration in the pin controller ops like this:

.. code-block:: c

        #include <linux/pinctrl/pinconf.h>
        #include <linux/pinctrl/pinctrl.h>

        #include "platform_x_pindefs.h"

        static int foo_pin_config_get(struct pinctrl_dev *pctldev,
                                      unsigned int offset,
                                      unsigned long *config)
        {
                struct my_conftype conf;

                /* ... Find setting for pin @ offset ... */

                *config = (unsigned long) conf;
        }

        static int foo_pin_config_set(struct pinctrl_dev *pctldev,
                                      unsigned int offset,
                                      unsigned long config)
        {
                struct my_conftype *conf = (struct my_conftype *) config;

                switch (conf) {
                        case PLATFORM_X_PULL_UP:
                        ...
                        break;
                }
        }

        static int foo_pin_config_group_get(struct pinctrl_dev *pctldev,
                                            unsigned selector,
                                            unsigned long *config)
        {
                ...
        }

        static int foo_pin_config_group_set(struct pinctrl_dev *pctldev,
                                            unsigned selector,
                                            unsigned long config)
        {
                ...
        }

        static struct pinconf_ops foo_pconf_ops = {
                .pin_config_get = foo_pin_config_get,
                .pin_config_set = foo_pin_config_set,
                .pin_config_group_get = foo_pin_config_group_get,
                .pin_config_group_set = foo_pin_config_group_set,
        };

        /* Pin config operations are handled by some pin controller */
        static struct pinctrl_desc foo_desc = {
                ...
                .confops = &foo_pconf_ops,
        };

GPIO controller와 pin controller의 range mapping

GPIO subsystem과 pinctrl subsystem은 서로 직교하지만 같은 물리 pin을 가리킬 수 있으므로 두 번호 공간의 mapping이 필요합니다. `struct pinctrl_gpio_range`는 GPIO chip, 시작 GPIO 번호, 대응하는 pin controller 번호, range 길이, 식별자와 이름을 연결합니다.

예에서 chip A의 GPIO 32..47은 pin 32..47에 일대일로 대응하고, chip B의 GPIO 48..55는 pin 64..71에 대응합니다. 번호가 연속되지 않는 하드웨어는 `{ 14, 1, 22, 17, 10, 8, 6, 2 }` 같은 explicit pin array를 range에 지정할 수 있습니다. group에 근거한 매핑이 필요하면 `pinctrl_get_group_pins()`로 이름에서 pin 배열을 얻습니다.

callback에는 어느 GPIO range에서 요청이 왔는지 구분할 수 있도록 range ID가 전달됩니다. 예전의 `pinctrl_add_gpio_range()` 방식은 DEPRECATED이며 새 Device Tree 기술에서는 firmware mapping을 사용해야 합니다. 세부 binding은 `Documentation/devicetree/bindings/gpio/gpio.txt`의 section 2.1을 따릅니다.

Interaction with the GPIO subsystem
===================================

The GPIO drivers may want to perform operations of various types on the same
physical pins that are also registered as pin controller pins.

First and foremost, the two subsystems can be used as completely orthogonal,
see the section named `Pin control requests from drivers`_ and
`Drivers needing both pin control and GPIOs`_ below for details. But in some
situations a cross-subsystem mapping between pins and GPIOs is needed.

Since the pin controller subsystem has its pinspace local to the pin controller
we need a mapping so that the pin control subsystem can figure out which pin
controller handles control of a certain GPIO pin. Since a single pin controller
may be muxing several GPIO ranges (typically SoCs that have one set of pins,
but internally several GPIO silicon blocks, each modelled as a struct
gpio_chip) any number of GPIO ranges can be added to a pin controller instance
like this:

.. code-block:: c

        #include <linux/gpio/driver.h>

        #include <linux/pinctrl/pinctrl.h>

        struct gpio_chip chip_a;
        struct gpio_chip chip_b;

        static struct pinctrl_gpio_range gpio_range_a = {
                .name = "chip a",
                .id = 0,
                .base = 32,
                .pin_base = 32,
                .npins = 16,
                .gc = &chip_a,
        };

        static struct pinctrl_gpio_range gpio_range_b = {
                .name = "chip b",
                .id = 0,
                .base = 48,
                .pin_base = 64,
                .npins = 8,
                .gc = &chip_b;
        };

        int __init foo_init(void)
        {
                struct pinctrl_dev *pctl;
                ...
                pinctrl_add_gpio_range(pctl, &gpio_range_a);
                pinctrl_add_gpio_range(pctl, &gpio_range_b);
                ...
        }

So this complex system has one pin controller handling two different
GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
"chip b" have different ``pin_base``, which means a start pin number of the
GPIO range.

The GPIO range of "chip a" starts from the GPIO base of 32 and actual
pin range also starts from 32. However "chip b" has different starting
offset for the GPIO range and pin range. The GPIO range of "chip b" starts
from GPIO number 48, while the pin range of "chip b" starts from 64.

We can convert a gpio number to actual pin number using this ``pin_base``.
They are mapped in the global GPIO pin space at:

chip a:
 - GPIO range : [32 .. 47]
 - pin range  : [32 .. 47]
chip b:
 - GPIO range : [48 .. 55]
 - pin range  : [64 .. 71]

The above examples assume the mapping between the GPIOs and pins is
linear. If the mapping is sparse or haphazard, an array of arbitrary pin
numbers can be encoded in the range like this:

.. code-block:: c

        static const unsigned int range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };

        static struct pinctrl_gpio_range gpio_range = {
                .name = "chip",
                .id = 0,
                .base = 32,
                .pins = &range_pins,
                .npins = ARRAY_SIZE(range_pins),
                .gc = &chip,
        };

In this case the ``pin_base`` property will be ignored. If the name of a pin
group is known, the pins and npins elements of the above structure can be
initialised using the function ``pinctrl_get_group_pins()``, e.g. for pin
group "foo":

.. code-block:: c

        pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);

When GPIO-specific functions in the pin control subsystem are called, these
ranges will be used to look up the appropriate pin controller by inspecting
and matching the pin to the pin ranges across all controllers. When a
pin controller handling the matching range is found, GPIO-specific functions
will be called on that specific pin controller.

For all functionalities dealing with pin biasing, pin muxing etc, the pin
controller subsystem will look up the corresponding pin number from the passed
in gpio number, and use the range's internals to retrieve a pin number. After
that, the subsystem passes it on to the pin control driver, so the driver
will get a pin number into its handled number range. Further it is also passed
the range ID value, so that the pin controller knows which range it should
deal with.

Calling ``pinctrl_add_gpio_range()`` from pinctrl driver is DEPRECATED. Please see
section 2.1 of ``Documentation/devicetree/bindings/gpio/gpio.txt`` on how to bind
pinctrl and gpio drivers.

pin multiplexing의 개념과 충돌

PINMUX는 여러 내부 주변장치 신호가 제한된 외부 pin을 공유하도록 switching matrix를 제어하는 기능입니다. kernel 내부에서 `pinmux_*` 접두사는 이 하위 계층을 위해 예약되어 있으므로 다른 subsystem이 임의로 사용해서는 안 됩니다.

8x8 PGA 예에서 SPI는 A8·A7·A6·A5를 사용할 수 있고 I2C는 A5·B5를 사용하므로 동시에 선택하면 A5에서 충돌합니다. 같은 SPI function을 G4·G3·G2·G1로 옮기는 대체 group을 선택하면 충돌을 피할 수 있습니다. MMC는 bottom row에서 2-bit, 4-bit, 8-bit 폭으로 확장될 수 있어 선택한 폭에 따라 SPI의 대체 group과 다시 겹칠 수 있습니다.

아무 peripheral function에도 할당하지 않은 pin은 대개 GPIO로 사용할 수 있지만, 이는 controller의 mux topology와 GPIO tap 위치에 따라 달라집니다. 따라서 datasheet의 가능성뿐 아니라 driver가 노출한 function/group 조합과 GPIO range를 기준으로 판단해야 합니다.

PINMUX interfaces
=================

These calls use the pinmux_* naming prefix.  No other calls should use that
prefix.


What is pinmuxing?
==================

PINMUX, also known as padmux, ballmux, alternate functions or mission modes
is a way for chip vendors producing some kind of electrical packages to use
a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
functions, depending on the application. By "application" in this context
we usually mean a way of soldering or wiring the package into an electronic
system, even though the framework makes it possible to also change the function
at runtime.

Here is an example of a PGA (Pin Grid Array) chip seen from underneath::

        A   B   C   D   E   F   G   H
      +---+
   8  | o | o   o   o   o   o   o   o
      |   |
   7  | o | o   o   o   o   o   o   o
      |   |
   6  | o | o   o   o   o   o   o   o
      +---+---+
   5  | o | o | o   o   o   o   o   o
      +---+---+               +---+
   4    o   o   o   o   o   o | o | o
                              |   |
   3    o   o   o   o   o   o | o | o
                              |   |
   2    o   o   o   o   o   o | o | o
      +-------+-------+-------+---+---+
   1  | o   o | o   o | o   o | o | o |
      +-------+-------+-------+---+---+

This is not tetris. The game to think of is chess. Not all PGA/BGA packages
are chessboard-like, big ones have "holes" in some arrangement according to
different design patterns, but we're using this as a simple example. Of the
pins you see some will be taken by things like a few VCC and GND to feed power
to the chip, and quite a few will be taken by large ports like an external
memory interface. The remaining pins will often be subject to pin multiplexing.

The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
pinctrl_register_pins() and a suitable data set as shown earlier.

In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
we cannot use the SPI port and I2C port at the same time. However in the inside
of the package the silicon performing the SPI logic can alternatively be routed
out on pins { G4, G3, G2, G1 }.

On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
port on pins { G4, G3, G2, G1 } of course.

This way the silicon blocks present inside the chip can be multiplexed "muxed"
out on different pin ranges. Often contemporary SoC (systems on chip) will
contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
different pins by pinmux settings.

Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
common to be able to use almost any pin as a GPIO pin if it is not currently
in use by some other I/O port.

function·group·mapping 규약

pinctrl 드라이버는 controller가 제공하는 FUNCTIONS를 열거합니다. function은 `drivers/pinctrl` 관점의 논리 기능이며, 하나 이상의 허용된 PIN GROUPS와 연결됩니다. 예를 들어 `spi0`는 두 group 중 하나를 사용할 수 있고 `i2c0`는 한 group만 사용할 수 있습니다. 실제 mux 선택은 function과 group의 쌍으로 완전히 식별됩니다.

board 또는 firmware mapping은 state name, pin controller, consumer device, function, 선택적 group을 연결합니다. group을 생략할 수 있는 경우에도 function이 선택 가능한 group을 명확히 열거해야 하며, resource 획득은 first-come, first-served이므로 이미 점유한 pin과 충돌하는 state는 거부됩니다.

pad와 package ball은 항상 일대일이 아닐 수 있습니다. controller가 직접 제어하는 개체가 pad라면 pad 번호를 pin 번호로 삼고, package ball과의 차이는 이름 또는 board mapping에서 설명해야 합니다.

현재 pinmux core는 function이 선택 가능한 group 목록을 드라이버가 완전하게 제공한다는 가정을 사용합니다. hardware가 허용하는 조합을 누락하면 유효한 board state를 표현할 수 없으므로 모든 function-to-group 선택지를 노출해야 합니다.

Pinmux conventions
==================

The purpose of the pinmux functionality in the pin controller subsystem is to
abstract and provide pinmux settings to the devices you choose to instantiate
in your machine configuration. It is inspired by the clk, GPIO and regulator
subsystems, so devices will request their mux setting, but it's also possible
to request a single pin for e.g. GPIO.

The conventions are:

- FUNCTIONS can be switched in and out by a driver residing with the pin
  control subsystem in the ``drivers/pinctrl`` directory of the kernel. The
  pin control driver knows the possible functions. In the example above you can
  identify three pinmux functions, one for spi, one for i2c and one for mmc.

- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
  In this case the array could be something like: { spi0, i2c0, mmc0 }
  for the three available functions.

- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
  function is *always* associated with a certain set of pin groups, could
  be just a single one, but could also be many. In the example above the
  function i2c is associated with the pins { A5, B5 }, enumerated as
  { 24, 25 } in the controller pin space.

  The Function spi is associated with pin groups { A8, A7, A6, A5 }
  and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
  { 38, 46, 54, 62 } respectively.

  Group names must be unique per pin controller, no two groups on the same
  controller may have the same name.

- The combination of a FUNCTION and a PIN GROUP determine a certain function
  for a certain set of pins. The knowledge of the functions and pin groups
  and their machine-specific particulars are kept inside the pinmux driver,
  from the outside only the enumerators are known, and the driver core can
  request:

  - The name of a function with a certain selector (>= 0)
  - A list of groups associated with a certain function
  - That a certain group in that list to be activated for a certain function

  As already described above, pin groups are in turn self-descriptive, so
  the core will retrieve the actual pin range in a certain group from the
  driver.

- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
  device by the board file, device tree or similar machine setup configuration
  mechanism, similar to how regulators are connected to devices, usually by
  name. Defining a pin controller, function and group thus uniquely identify
  the set of pins to be used by a certain device. (If only one possible group
  of pins is available for the function, no group name need to be supplied -
  the core will simply select the first and only group available.)

  In the example case we can define that this particular machine shall
  use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
  fi2c0 group gi2c0, on the primary pin controller, we get mappings
  like these:

  .. code-block:: c

        {
                {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
                {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0},
        }

  Every map must be assigned a state name, pin controller, device and
  function. The group is not compulsory - if it is omitted the first group
  presented by the driver as applicable for the function will be selected,
  which is useful for simple cases.

  It is possible to map several groups to the same combination of device,
  pin controller and function. This is for cases where a certain function on
  a certain pin controller may use different sets of pins in different
  configurations.

- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
  PIN CONTROLLER are provided on a first-come first-serve basis, so if some
  other device mux setting or GPIO pin request has already taken your physical
  pin, you will be denied the use of it. To get (activate) a new setting, the
  old one has to be put (deactivated) first.

Sometimes the documentation and hardware registers will be oriented around
pads (or "fingers") rather than pins - these are the soldering surfaces on the
silicon inside the package, and may or may not match the actual number of
pins/balls underneath the capsule. Pick some enumeration that makes sense to
you. Define enumerators only for the pins you can control if that makes sense.

Assumptions:

We assume that the number of possible function maps to pin groups is limited by
the hardware. I.e. we assume that there is no system where any function can be
mapped to any pin, like in a phone exchange. So the available pin groups for
a certain function will be limited to a few choices (say up to eight or so),
not hundreds or any amount of choices. This is the characteristic we have found
by inspecting available pinmux hardware, and a necessary assumption since we
expect pinmux drivers to present *all* possible function vs pin group mappings
to the subsystem.

pinmux 드라이버 callback과 core 충돌 방지

pinctrl core는 동일 pin을 요구하는 mux 설정이 겹치지 않게 reservation을 관리하지만, 전압·drive mode·동시 switching 제한처럼 하드웨어 고유의 전기적 제약은 controller 드라이버가 검사해야 합니다.

예제 controller는 `PINCTRL_PINGROUP()`으로 `spi0_0_grp`의 `{0,8,16,24}`, `spi0_1_grp`의 `{38,46,54,62}`, `i2c0_grp`의 `{24,25}`, MMC의 `{56,57}`, `{58,59}`, `{60,61,62,63}`를 선언합니다. `PINCTRL_PINFUNCTION()`으로 `spi0`, `i2c0`, `mmc0` function을 각 허용 group 목록과 연결합니다.

`struct pinmux_ops`의 필수 흐름은 `.get_functions_count()`, `.get_function_name()`, `.get_function_groups()`, `.set_mux()`입니다. `.set_mux()`는 core가 선택한 function selector와 group selector를 실제 register 설정으로 변환합니다. `.strict = true`는 동일 pin에 대한 GPIO와 mux 사용을 동시에 허용하지 않는 controller에 사용합니다.

이 배치에서는 mux 0과 2가 pin 24를 공유하고 mux 1과 5가 pin 62를 공유합니다. 첫 state가 pin을 예약한 동안 충돌하는 두 번째 state를 선택하면 core가 driver callback 전에 거부합니다.

Pinmux drivers
==============

The pinmux core takes care of preventing conflicts on pins and calling
the pin controller driver to execute different settings.

It is the responsibility of the pinmux driver to impose further restrictions
(say for example infer electronic limitations due to load, etc.) to determine
whether or not the requested function can actually be allowed, and in case it
is possible to perform the requested mux setting, poke the hardware so that
this happens.

Pinmux drivers are required to supply a few callback functions, some are
optional. Usually the ``.set_mux()`` function is implemented, writing values into
some certain registers to activate a certain mux setting for a certain pin.

A simple driver for the above example will work by setting bits 0, 1, 2, 3, 4, or 5
into some register named MUX to select a certain function with a certain
group of pins would work something like this:

.. code-block:: c

        #include <linux/pinctrl/pinctrl.h>
        #include <linux/pinctrl/pinmux.h>

        static const unsigned int spi0_0_pins[] = { 0, 8, 16, 24 };
        static const unsigned int spi0_1_pins[] = { 38, 46, 54, 62 };
        static const unsigned int i2c0_pins[] = { 24, 25 };
        static const unsigned int mmc0_1_pins[] = { 56, 57 };
        static const unsigned int mmc0_2_pins[] = { 58, 59 };
        static const unsigned int mmc0_3_pins[] = { 60, 61, 62, 63 };

        static const struct pingroup foo_groups[] = {
                PINCTRL_PINGROUP("spi0_0_grp", spi0_0_pins, ARRAY_SIZE(spi0_0_pins)),
                PINCTRL_PINGROUP("spi0_1_grp", spi0_1_pins, ARRAY_SIZE(spi0_1_pins)),
                PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)),
                PINCTRL_PINGROUP("mmc0_1_grp", mmc0_1_pins, ARRAY_SIZE(mmc0_1_pins)),
                PINCTRL_PINGROUP("mmc0_2_grp", mmc0_2_pins, ARRAY_SIZE(mmc0_2_pins)),
                PINCTRL_PINGROUP("mmc0_3_grp", mmc0_3_pins, ARRAY_SIZE(mmc0_3_pins)),
        };

        static int foo_get_groups_count(struct pinctrl_dev *pctldev)
        {
                return ARRAY_SIZE(foo_groups);
        }

        static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
                                              unsigned int selector)
        {
                return foo_groups[selector].name;
        }

        static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
                                      const unsigned int **pins,
                                      unsigned int *npins)
        {
                *pins = foo_groups[selector].pins;
                *npins = foo_groups[selector].npins;
                return 0;
        }

        static struct pinctrl_ops foo_pctrl_ops = {
                .get_groups_count = foo_get_groups_count,
                .get_group_name = foo_get_group_name,
                .get_group_pins = foo_get_group_pins,
        };

        static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
        static const char * const i2c0_groups[] = { "i2c0_grp" };
        static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", "mmc0_3_grp" };

        static const struct pinfunction foo_functions[] = {
                PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)),
                PINCTRL_PINFUNCTION("i2c0", i2c0_groups, ARRAY_SIZE(i2c0_groups)),
                PINCTRL_PINFUNCTION("mmc0", mmc0_groups, ARRAY_SIZE(mmc0_groups)),
        };

        static int foo_get_functions_count(struct pinctrl_dev *pctldev)
        {
                return ARRAY_SIZE(foo_functions);
        }

        static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned int selector)
        {
                return foo_functions[selector].name;
        }

        static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
                                  const char * const **groups,
                                  unsigned int * const ngroups)
        {
                *groups = foo_functions[selector].groups;
                *ngroups = foo_functions[selector].ngroups;
                return 0;
        }

        static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
                               unsigned int group)
        {
                u8 regbit = BIT(group);

                writeb((readb(MUX) | regbit), MUX);
                return 0;
        }

        static struct pinmux_ops foo_pmxops = {
                .get_functions_count = foo_get_functions_count,
                .get_function_name = foo_get_fname,
                .get_function_groups = foo_get_groups,
                .set_mux = foo_set_mux,
                .strict = true,
        };

        /* Pinmux operations are handled by some pin controller */
        static struct pinctrl_desc foo_desc = {
                ...
                .pctlops = &foo_pctrl_ops,
                .pmxops = &foo_pmxops,
        };

In the example activating muxing 0 and 2 at the same time setting bits
0 and 2, uses pin 24 in common so they would collide. All the same for
the muxes 1 and 5, which have pin 62 in common.

The beauty of the pinmux subsystem is that since it keeps track of all
pins and who is using them, it will already have denied an impossible
request like that, so the driver does not need to worry about such
things - when it gets a selector passed in, the pinmux subsystem makes
sure no other device or GPIO assignment is already using the selected
pins. Thus bits 0 and 2, or 1 and 5 in the control register will never
be set at the same time.

All the above functions are mandatory to implement for a pinmux driver.

gpiolib에서만 호출하는 pinmux/GPIO API

이 절의 GPIO API는 datasheet에 쓰인 추상적인 'GPIO mode'가 아니라 `<linux/gpio/consumer.h>`를 통해 관리되는 실제 kernel GPIO를 뜻합니다. `pinctrl_gpio_request()`와 `pinctrl_gpio_free()`는 gpiolib의 `.request()`·`.free()` callback에서만 호출해야 합니다.

마찬가지로 input/output 방향 변경 API는 gpiolib direction callback 안에서만 사용합니다. platform driver나 개별 peripheral driver가 mux된 pin을 얻기 위해 이 API를 직접 호출해서는 안 됩니다.

controller는 필요에 따라 `pinmux_ops`의 `.gpio_request_enable()`, `.gpio_disable_free()`, `.gpio_set_direction()`을 구현합니다. 명시적인 GPIO group 이름이 없으면 core는 `gpioN` 형식의 이름으로 fallback할 수 있습니다.

Pin control interaction with the GPIO subsystem
===============================================

Note that the following implies that the use case is to use a certain pin
from the Linux kernel using the API in ``<linux/gpio/consumer.h>`` with gpiod_get()
and similar functions. There are cases where you may be using something
that your datasheet calls "GPIO mode", but actually is just an electrical
configuration for a certain device. See the section below named
`GPIO mode pitfalls`_ for more details on this scenario.

The public pinmux API contains two functions named ``pinctrl_gpio_request()``
and ``pinctrl_gpio_free()``. These two functions shall *ONLY* be called from
gpiolib-based drivers as part of their ``.request()`` and ``.free()`` semantics.
Likewise the ``pinctrl_gpio_direction_input()`` / ``pinctrl_gpio_direction_output()``
shall only be called from within respective ``.direction_input()`` /
``.direction_output()`` gpiolib implementation.

NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
that driver request proper muxing and other control for its pins.

The function list could become long, especially if you can convert every
individual pin into a GPIO pin independent of any other pins, and then try
the approach to define every pin as a function.

In this case, the function array would become 64 entries for each GPIO
setting and then the device functions.

For this reason there are two functions a pin control driver can implement
to enable only GPIO on an individual pin: ``.gpio_request_enable()`` and
``.gpio_disable_free()``.

This function will pass in the affected GPIO range identified by the pin
controller core, so you know which GPIO pins are being affected by the request
operation.

If your driver needs to have an indication from the framework of whether the
GPIO pin shall be used for input or output you can implement the
``.gpio_set_direction()`` function. As described this shall be called from the
gpiolib driver and the affected GPIO range, pin offset and desired direction
will be passed along to this function.

Alternatively to using these special functions, it is fully allowed to use
named functions for each GPIO pin, the ``pinctrl_gpio_request()`` will attempt to
obtain the function "gpioN" where "N" is the global GPIO pin number if no
special GPIO-handler is registered.

datasheet GPIO mode의 두 구조와 subsystem 경계

datasheet의 'GPIO mode'는 Linux GPIO subsystem을 뜻하지 않을 수 있습니다. 어떤 controller에서는 pad가 pinmux를 거쳐 SPI·I2C·MMC·GPIO 가운데 하나로 연결되고 pin configuration 블록은 이 경로와 별도로 전기 특성을 설정합니다. 이 구조에서는 GPIO가 다른 function과 동일한 mux 선택지이며 `.strict`로 동시 사용을 막는 것이 자연스럽습니다.

다른 controller에서는 GPIO block이 pad와 pinmux 사이의 신호를 옆에서 tap합니다. 이 구조의 GPIO input은 peripheral 신호를 관찰할 수 있고 output enable은 활성 peripheral을 방해할 수 있습니다. 하드웨어상 동시 접근이 가능해도 안전하지 않다면 역시 `.strict`를 사용해 mux owner와 GPIO owner가 같은 pin을 동시에 요청하지 못하게 해야 합니다.

책임 경계는 명확합니다. pull, drive strength, output level 같은 electrical configuration은 pinctrl의 pinconf가 맡고, SPI/UART/I2C 같은 signal routing은 pinctrl의 pinmux가 맡으며, runtime GPIO value·input/output direction은 GPIO subsystem이 맡습니다. GPIO interrupt는 GPIO driver와 irqchip 계층에서 구현합니다.

GPIO mode pitfalls
==================

Due to the naming conventions used by hardware engineers, where "GPIO"
is taken to mean different things than what the kernel does, the developer
may be confused by a datasheet talking about a pin being possible to set
into "GPIO mode". It appears that what hardware engineers mean with
"GPIO mode" is not necessarily the use case that is implied in the kernel
interface ``<linux/gpio/consumer.h>``: a pin that you grab from kernel code and then
either listen for input or drive high/low to assert/deassert some
external line.

Rather hardware engineers think that "GPIO mode" means that you can
software-control a few electrical properties of the pin that you would
not be able to control if the pin was in some other mode, such as muxed in
for a device.

The GPIO portions of a pin and its relation to a certain pin controller
configuration and muxing logic can be constructed in several ways. Here
are two examples.

Example **(A)**::

                       pin config
                       logic regs
                       |               +- SPI
     Physical pins --- pad --- pinmux -+- I2C
                               |       +- mmc
                               |       +- GPIO
                               pin
                               multiplex
                               logic regs

Here some electrical properties of the pin can be configured no matter
whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
pin, you can also drive it high/low from "GPIO" registers.
Alternatively, the pin can be controlled by a certain peripheral, while
still applying desired pin config properties. GPIO functionality is thus
orthogonal to any other device using the pin.

In this arrangement the registers for the GPIO portions of the pin controller,
or the registers for the GPIO hardware module are likely to reside in a
separate memory range only intended for GPIO driving, and the register
range dealing with pin config and pin multiplexing get placed into a
different memory range and a separate section of the data sheet.

A flag "strict" in struct pinmux_ops is available to check and deny
simultaneous access to the same pin from GPIO and pin multiplexing
consumers on hardware of this type. The pinctrl driver should set this flag
accordingly.

Example **(B)**::

                       pin config
                       logic regs
                       |               +- SPI
     Physical pins --- pad --- pinmux -+- I2C
                       |       |       +- mmc
                       |       |
                       GPIO    pin
                               multiplex
                               logic regs

In this arrangement, the GPIO functionality can always be enabled, such that
e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
pulsed out. It is likely possible to disrupt the traffic on the pin by doing
wrong things on the GPIO block, as it is never really disconnected. It is
possible that the GPIO, pin config and pin multiplex registers are placed into
the same memory range and the same section of the data sheet, although that
need not be the case.

In some pin controllers, although the physical pins are designed in the same
way as (B), the GPIO function still can't be enabled at the same time as the
peripheral functions. So again the "strict" flag should be set, denying
simultaneous activation by GPIO and other muxed in devices.

From a kernel point of view, however, these are different aspects of the
hardware and shall be put into different subsystems:

- Registers (or fields within registers) that control electrical
  properties of the pin such as biasing and drive strength should be
  exposed through the pinctrl subsystem, as "pin configuration" settings.

- Registers (or fields within registers) that control muxing of signals
  from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
  be exposed through the pinctrl subsystem, as mux functions.

- Registers (or fields within registers) that control GPIO functionality
  such as setting a GPIO's output value, reading a GPIO's input value, or
  setting GPIO pin direction should be exposed through the GPIO subsystem,
  and if they also support interrupt capabilities, through the irqchip
  abstraction.

Depending on the exact HW register design, some functions exposed by the
GPIO subsystem may call into the pinctrl subsystem in order to
coordinate register settings across HW modules. In particular, this may
be needed for HW with separate GPIO and pin controller HW modules, where
e.g. GPIO direction is determined by a register in the pin controller HW
module rather than the GPIO HW module.

Electrical properties of the pin such as biasing and drive strength
may be placed at some pin-specific register in all cases or as part
of the GPIO register in case (B) especially. This doesn't mean that such
properties necessarily pertain to what the Linux kernel calls "GPIO".

UART sleep 상태와 PIN_CONFIG_LEVEL

UART TX를 suspend 중 low로 유지하려고 UART pin을 잠시 GPIO로 요청하고 값을 내리는 방식은 잘못된 subsystem 경계를 만들고 ownership race를 유발합니다. 이 요구는 signal routing 변경이 아니라 pad의 output level과 electrical mode 변경이므로 pin configuration state로 표현해야 합니다.

드라이버는 `pinctrl_lookup_state()`로 기본 UART state `u0`와 sleep state `gpio-mode`를 찾고, `pinctrl_select_state()`로 전환합니다. mapping에서 `u0`는 UART function과 push-pull 설정을 선택하고, `gpio-mode`는 같은 pin에 `PIN_CONFIG_LEVEL` low를 적용합니다. 이름에 GPIO가 들어가더라도 gpiod request/value cycle을 수행하는 것이 아닙니다.

datasheet의 low power mode도 같은 원칙으로 판단합니다. pin을 Linux GPIO line으로 사용할 목적이 아니라 bias, level, input buffer, output driver를 절전 상태로 바꾸는 목적이면 GPIO API가 아니라 pinconf state를 사용합니다.

Example: a pin is usually muxed in to be used as a UART TX line. But during
system sleep, we need to put this pin into "GPIO mode" and ground it.

If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
to think that you need to come up with something really complex, that the
pin shall be used for UART TX and GPIO at the same time, that you will grab
a pin control handle and set it to a certain state to enable UART TX to be
muxed in, then twist it over to GPIO mode and use gpiod_direction_output()
to drive it low during sleep, then mux it over to UART TX again when you
wake up and maybe even gpiod_get() / gpiod_put() as part of this cycle. This
all gets very complicated.

The solution is to not think that what the datasheet calls "GPIO mode"
has to be handled by the ``<linux/gpio/consumer.h>`` interface. Instead view this as
a certain pin config setting. Look in e.g. ``<linux/pinctrl/pinconf-generic.h>``
and you find this in the documentation:

  PIN_CONFIG_LEVEL:
     this will configure the pin in output, use argument
     1 to indicate high level, argument 0 to indicate low level.

So it is perfectly possible to push a pin into "GPIO mode" and drive the
line low as part of the usual pin control map. So for example your UART
driver may look like this:

.. code-block:: c

        #include <linux/pinctrl/consumer.h>

        struct pinctrl          *pinctrl;
        struct pinctrl_state    *pins_default;
        struct pinctrl_state    *pins_sleep;

        pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
        pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);

        /* Normal mode */
        retval = pinctrl_select_state(pinctrl, pins_default);

        /* Sleep mode */
        retval = pinctrl_select_state(pinctrl, pins_sleep);

And your machine configuration may look like this:

.. code-block:: c

        static unsigned long uart_default_mode[] = {
                PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
        };

        static unsigned long uart_sleep_mode[] = {
                PIN_CONF_PACKED(PIN_CONFIG_LEVEL, 0),
        };

        static struct pinctrl_map pinmap[] __initdata = {
                PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
                                  "u0_group", "u0"),
                PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
                                    "UART_TX_PIN", uart_default_mode),
                PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
                                  "u0_group", "gpio-mode"),
                PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
                                    "UART_TX_PIN", uart_sleep_mode),
        };

        foo_init(void)
        {
                pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
        }

Here the pins we want to control are in the "u0_group" and there is some
function called "u0" that can be enabled on this group of pins, and then
everything is UART business as usual. But there is also some function
named "gpio-mode" that can be mapped onto the same pins to move them into
GPIO mode.

This will give the desired effect without any bogus interaction with the
GPIO subsystem. It is just an electrical configuration used by that device
when going to sleep, it might imply that the pin is set into something the
datasheet calls "GPIO mode", but that is not the point: it is still used
by that UART device to control the pins that pertain to that very UART
driver, putting them into modes needed by the UART. GPIO in the Linux
kernel sense are just some 1-bit line, and is a different use case.

How the registers are poked to attain the push or pull, and output low
configuration and the muxing of the "u0" or "gpio-mode" group onto these
pins is a question for the driver.

Some datasheets will be more helpful and refer to the "GPIO mode" as
"low power mode" rather than anything to do with GPIO. This often means
the same thing electrically speaking, but in this latter case the
software engineers will usually quickly identify that this is some
specific muxing or configuration rather than anything related to the GPIO
API.

board·machine mapping과 configuration macro

board 또는 machine 코드는 consumer device와 pin controller 사이의 mapping table을 등록할 수 있습니다. 각 record는 state name, controller, consumer device, function, group을 기술하며 `pinctrl_register_mappings()`로 core에 전달합니다.

단일 mux mapping은 `PIN_MAP_MUX_GROUP()` helper로 만들 수 있습니다. pin configuration은 group 대상 `PIN_MAP_CONFIGS_GROUP()` 또는 개별 pin 대상 `PIN_MAP_CONFIGS_PIN()`으로 config 배열을 state에 연결합니다. 한 state에 mux record와 config record를 함께 두면 선택 시 모두 적용됩니다.

driver가 반드시 특정 named state를 찾지만 board에서 실제 pin 설정이 필요하지 않은 경우 `PIN_MAP_DUMMY_STATE()`를 등록할 수 있습니다. dummy state는 lookup 계약을 만족하지만 hardware register를 바꾸지 않습니다.

Board/machine configuration
===========================

Boards and machines define how a certain complete running system is put
together, including how GPIOs and devices are muxed, how regulators are
constrained and how the clock tree looks. Of course pinmux settings are also
part of this.

A pin controller configuration for a machine looks pretty much like a simple
regulator configuration, so for the example array above we want to enable i2c
and spi on the second function mapping:

.. code-block:: c

        #include <linux/pinctrl/machine.h>

        static const struct pinctrl_map mapping[] __initconst = {
                {
                        .dev_name = "foo-spi.0",
                        .name = PINCTRL_STATE_DEFAULT,
                        .type = PIN_MAP_TYPE_MUX_GROUP,
                        .ctrl_dev_name = "pinctrl-foo",
                        .data.mux.function = "spi0",
                },
                {
                        .dev_name = "foo-i2c.0",
                        .name = PINCTRL_STATE_DEFAULT,
                        .type = PIN_MAP_TYPE_MUX_GROUP,
                        .ctrl_dev_name = "pinctrl-foo",
                        .data.mux.function = "i2c0",
                },
                {
                        .dev_name = "foo-mmc.0",
                        .name = PINCTRL_STATE_DEFAULT,
                        .type = PIN_MAP_TYPE_MUX_GROUP,
                        .ctrl_dev_name = "pinctrl-foo",
                        .data.mux.function = "mmc0",
                },
        };

The dev_name here matches to the unique device name that can be used to look
up the device struct (just like with clockdev or regulators). The function name
must match a function provided by the pinmux driver handling this pin range.

As you can see we may have several pin controllers on the system and thus
we need to specify which one of them contains the functions we wish to map.

You register this pinmux mapping to the pinmux subsystem by simply:

.. code-block:: c

       ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));

Since the above construct is pretty common there is a helper macro to make
it even more compact which assumes you want to use pinctrl-foo and position
0 for mapping, for example:

.. code-block:: c

        static struct pinctrl_map mapping[] __initdata = {
                PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                                  "pinctrl-foo", NULL, "i2c0"),
        };

The mapping table may also contain pin configuration entries. It's common for
each pin/group to have a number of configuration entries that affect it, so
the table entries for configuration reference an array of config parameters
and values. An example using the convenience macros is shown below:

.. code-block:: c

        static unsigned long i2c_grp_configs[] = {
                FOO_PIN_DRIVEN,
                FOO_PIN_PULLUP,
        };

        static unsigned long i2c_pin_configs[] = {
                FOO_OPEN_COLLECTOR,
                FOO_SLEW_RATE_SLOW,
        };

        static struct pinctrl_map mapping[] __initdata = {
                PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                                  "pinctrl-foo", "i2c0", "i2c0"),
                PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                                      "pinctrl-foo", "i2c0", i2c_grp_configs),
                PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                                    "pinctrl-foo", "i2c0scl", i2c_pin_configs),
                PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
                                    "pinctrl-foo", "i2c0sda", i2c_pin_configs),
        };

Finally, some devices expect the mapping table to contain certain specific
named states. When running on hardware that doesn't need any pin controller
configuration, the mapping table must still contain those named states, in
order to explicitly indicate that the states were provided and intended to
be empty. Table entry macro ``PIN_MAP_DUMMY_STATE()`` serves the purpose of defining
a named state without causing any pin controller to be programmed:

.. code-block:: c

        static struct pinctrl_map mapping[] __initdata = {
                PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
        };

복합 state, 대체 위치, additive group

같은 function을 서로 다른 위치에 배치하려면 `spi0-pos-A`, `spi0-pos-B`처럼 state 이름을 구분하고 각 state를 다른 group에 연결합니다. consumer는 `devm_pinctrl_get()`으로 handle을 얻고 `pinctrl_lookup_state()`로 원하는 위치를 찾은 뒤 `pinctrl_select_state()`로 활성화합니다. 단축형 `devm_pinctrl_get_select()`는 handle 획득과 state 선택을 함께 수행합니다.

하나의 state가 여러 group을 동시에 활성화할 수도 있습니다. MMC의 2-bit 기본 group에 4-bit 확장 group, 다시 8-bit 확장 group을 더하는 additive 설계에서는 같은 state/controller/function/device를 공유하는 mapping record가 모두 선택됩니다. 따라서 8-bit state는 세 group을 함께 활성화해 전체 data bus를 구성합니다.

core는 state 이름 하나에 속한 모든 record를 모아 적용하므로, 일부 group만 선택될 것이라고 가정해서는 안 됩니다. group 간 충돌과 적용 순서는 mapping table과 driver의 하드웨어 제약을 함께 검토해야 합니다.

Complex mappings
================

As it is possible to map a function to different groups of pins an optional
.group can be specified like this:

.. code-block:: c

        ...
        {
                .dev_name = "foo-spi.0",
                .name = "spi0-pos-A",
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .function = "spi0",
                .group = "spi0_0_grp",
        },
        {
                .dev_name = "foo-spi.0",
                .name = "spi0-pos-B",
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .function = "spi0",
                .group = "spi0_1_grp",
        },
        ...

This example mapping is used to switch between two positions for spi0 at
runtime, as described further below under the heading `Runtime pinmuxing`_.

Further it is possible for one named state to affect the muxing of several
groups of pins, say for example in the mmc0 example above, where you can
additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
three groups for a total of 2 + 2 + 4 = 8 pins (for an 8-bit MMC bus as is the
case), we define a mapping like this:

.. code-block:: c

        ...
        {
                .dev_name = "foo-mmc.0",
                .name = "2bit"
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .function = "mmc0",
                .group = "mmc0_1_grp",
        },
        {
                .dev_name = "foo-mmc.0",
                .name = "4bit"
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .function = "mmc0",
                .group = "mmc0_1_grp",
        },
        {
                .dev_name = "foo-mmc.0",
                .name = "4bit"
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .function = "mmc0",
                .group = "mmc0_2_grp",
        },
        {
                .dev_name = "foo-mmc.0",
                .name = "8bit"
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .function = "mmc0",
                .group = "mmc0_1_grp",
        },
        {
                .dev_name = "foo-mmc.0",
                .name = "8bit"
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .function = "mmc0",
                .group = "mmc0_2_grp",
        },
        {
                .dev_name = "foo-mmc.0",
                .name = "8bit"
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .function = "mmc0",
                .group = "mmc0_3_grp",
        },
        ...

The result of grabbing this mapping from the device with something like
this (see next paragraph):

.. code-block:: c

        p = devm_pinctrl_get(dev);
        s = pinctrl_lookup_state(p, "8bit");
        ret = pinctrl_select_state(p, s);

or more simply:

.. code-block:: c

        p = devm_pinctrl_get_select(dev, "8bit");

Will be that you activate all the three bottom records in the mapping at
once. Since they share the same name, pin controller device, function and
device, and since we allow multiple groups to match to a single device, they
all get selected, and they all get enabled and disable simultaneously by the
pinmux core.

driver core의 표준 pinctrl state

driver core는 device를 bind할 때 `pinctrl_bind_pins()`로 표준 state를 준비합니다. 표준 이름은 `default`, `init`, `sleep`, `idle`이며 각각 probe 전 기본 설정, probe 중 초기 설정, system sleep, runtime idle 용도를 가집니다.

`init` state가 있으면 probe 전에 먼저 선택하고 probe가 끝난 뒤 `default`로 전환합니다. `init`가 없으면 probe 전에 `default`를 선택합니다. `sleep`과 `idle`은 자동으로 임의 시점에 적용되지 않으며 해당 PM helper 또는 driver PM 경로를 통해 선택합니다.

Pin control requests from drivers
=================================

When a device driver is about to probe, the device core attaches the
standard states if they are defined in the device tree by calling
``pinctrl_bind_pins()`` on these devices.
Possible standard state names are: "default", "init", "sleep" and "idle".

- if ``default`` is defined in the device tree, it is selected before
  device probe.

- if ``init`` and ``default`` are defined in the device tree, the "init"
  state is selected before the driver probe and the "default" state is
  selected after the driver probe.

- the ``sleep`` and ``idle`` states are for power management and can only
  be selected with the PM API bellow.

PM helper와 직접 state 제어 지침

PM 경로에서는 `pinctrl_pm_select_default_state()`, `pinctrl_pm_select_init_state()`, `pinctrl_pm_select_sleep_state()`, `pinctrl_pm_select_idle_state()`를 사용해 표준 state를 선택할 수 있습니다. system suspend는 sleep state를 선택하고, resume은 필요하면 init state를 거쳐 device resume을 수행한 뒤 default state로 돌아갑니다.

driver core가 default mapping과 bind 시점의 초기 전환을 처리하므로 일반 device driver가 같은 작업을 중복할 필요는 없습니다. 개별 driver가 pinctrl을 직접 다루는 방식은 권장되지 않지만, runtime에 실제 mux 위치나 electrical mode를 바꿔야 하는 device에는 예외적으로 필요합니다.

직접 state를 다룰 때도 표준 이름은 `PINCTRL_STATE_DEFAULT`, `PINCTRL_STATE_SLEEP`, `PINCTRL_STATE_INIT` 상수를 사용해 spelling과 의미를 통일해야 합니다.

PM interfaces
=================
PM runtime suspend/resume might need to execute the same init sequence as
during probe. Since the predefined states are already attached to the
device, the driver can activate these states explicitly with the
following helper functions:

- ``pinctrl_pm_select_default_state()``
- ``pinctrl_pm_select_init_state()``
- ``pinctrl_pm_select_sleep_state()``
- ``pinctrl_pm_select_idle_state()``

For example, if resuming the device depend on certain pinmux states

.. code-block:: c

        foo_suspend()
        {
                /* suspend device */
                ...

                pinctrl_pm_select_sleep_state(dev);
        }

        foo_resume()
        {
                pinctrl_pm_select_init_state(dev);

                /* resuming device */
                ...

                pinctrl_pm_select_default_state(dev);
        }

This way driver writers do not need to add any of the boilerplate code
of the type found below. However when doing fine-grained state selection
and not using the "default" state, you may have to do some device driver
handling of the pinctrl handles and states.

So if you just want to put the pins for a certain device into the default
state and be done with it, there is nothing you need to do besides
providing the proper mapping table. The device core will take care of
the rest.

Generally it is discouraged to let individual drivers get and enable pin
control. So if possible, handle the pin control in platform code or some other
place where you have access to all the affected struct device * pointers. In
some cases where a driver needs to e.g. switch between different mux mappings
at runtime this is not possible.

A typical case is if a driver needs to switch bias of pins from normal
operation and going to sleep, moving from the ``PINCTRL_STATE_DEFAULT`` to
``PINCTRL_STATE_SLEEP`` at runtime, re-biasing or even re-muxing pins to save
current in sleep mode.

Another case is when the pinctrl needs to switch to a certain mode during
probe and then revert to the default state at the end of probe. For example
a PINMUX may need to be configured as a GPIO during probe. In this case, use
``PINCTRL_STATE_INIT`` to switch state before probe, then move to
``PINCTRL_STATE_DEFAULT`` at the end of probe for normal operation.

driver 직접 요청 API의 context와 수명 규칙

runtime에 state를 직접 전환해야 하는 driver는 managed 흐름으로 `devm_pinctrl_get()`, `pinctrl_lookup_state()`, `pinctrl_select_state()`를 사용할 수 있습니다. `pinctrl_get()`은 firmware mapping을 parse하고 handle을 구성하므로 process context에서 호출해야 하며 느릴 수 있습니다. 자동 정리를 위해 `devm_pinctrl_get()`이 권장됩니다.

`pinctrl_lookup_state()`도 state record를 찾고 준비하므로 process context에서 느릴 수 있습니다. `pinctrl_select_state()`는 이론상 미리 준비된 state를 적용하는 빠른 경로지만 controller register가 slow bus 또는 IRQ-dependent bus에 있으면 non-blocking을 보장할 수 없습니다. atomic context에서 안전하다고 가정해서는 안 됩니다.

수명 API는 섞지 않습니다. plain `pinctrl_get()`은 반드시 plain `pinctrl_put()`과 짝지어야 합니다. managed `devm_pinctrl_get()`은 detach 때 자동으로 해제되며, 조기 해제가 필요할 때만 `devm_pinctrl_put()`을 사용합니다. managed handle에 plain put을 호출하면 안 됩니다. 할당된 handle과 state는 debugfs에서 확인할 수 있습니다.

controller가 아직 등록되지 않았다면 get은 `-EPROBE_DEFER`를 반환할 수 있습니다. driver는 지금까지 얻은 resource를 정리하고 probe를 반환해야 하며, core가 나중에 등록 순서가 충족되었을 때 probe를 다시 시도합니다.

A driver may request a certain control state to be activated, usually just the
default state like this:

.. code-block:: c

        #include <linux/pinctrl/consumer.h>

        struct foo_state {
        struct pinctrl *p;
        struct pinctrl_state *s;
        ...
        };

        foo_probe()
        {
                /* Allocate a state holder named "foo" etc */
                struct foo_state *foo = ...;
                int ret;

                foo->p = devm_pinctrl_get(&device);
                if (IS_ERR(foo->p)) {
                        ret = PTR_ERR(foo->p);
                        foo->p = NULL;
                        return ret;
                }

                foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
                if (IS_ERR(foo->s)) {
                        devm_pinctrl_put(foo->p);
                        return PTR_ERR(foo->s);
                }

                ret = pinctrl_select_state(foo->p, foo->s);
                if (ret < 0) {
                        devm_pinctrl_put(foo->p);
                        return ret;
                }
        }

This get/lookup/select/put sequence can just as well be handled by bus drivers
if you don't want each and every driver to handle it and you know the
arrangement on your bus.

The semantics of the pinctrl APIs are:

- ``pinctrl_get()`` is called in process context to obtain a handle to all pinctrl
  information for a given client device. It will allocate a struct from the
  kernel memory to hold the pinmux state. All mapping table parsing or similar
  slow operations take place within this API.

- ``devm_pinctrl_get()`` is a variant of pinctrl_get() that causes ``pinctrl_put()``
  to be called automatically on the retrieved pointer when the associated
  device is removed. It is recommended to use this function over plain
  ``pinctrl_get()``.

- ``pinctrl_lookup_state()`` is called in process context to obtain a handle to a
  specific state for a client device. This operation may be slow, too.

- ``pinctrl_select_state()`` programs pin controller hardware according to the
  definition of the state as given by the mapping table. In theory, this is a
  fast-path operation, since it only involved blasting some register settings
  into hardware. However, note that some pin controllers may have their
  registers on a slow/IRQ-based bus, so client devices should not assume they
  can call ``pinctrl_select_state()`` from non-blocking contexts.

- ``pinctrl_put()`` frees all information associated with a pinctrl handle.

- ``devm_pinctrl_put()`` is a variant of ``pinctrl_put()`` that may be used to
  explicitly destroy a pinctrl object returned by ``devm_pinctrl_get()``.
  However, use of this function will be rare, due to the automatic cleanup
  that will occur even without calling it.

  ``pinctrl_get()`` must be paired with a plain ``pinctrl_put()``.
  ``pinctrl_get()`` may not be paired with ``devm_pinctrl_put()``.
  ``devm_pinctrl_get()`` can optionally be paired with ``devm_pinctrl_put()``.
  ``devm_pinctrl_get()`` may not be paired with plain ``pinctrl_put()``.

Usually the pin control core handled the get/put pair and call out to the
device drivers bookkeeping operations, like checking available functions and
the associated pins, whereas ``pinctrl_select_state()`` pass on to the pin controller
driver which takes care of activating and/or deactivating the mux setting by
quickly poking some registers.

The pins are allocated for your device when you issue the ``devm_pinctrl_get()``
call, after this you should be able to see this in the debugfs listing of all
pins.

NOTE: the pinctrl system will return ``-EPROBE_DEFER`` if it cannot find the
requested pinctrl handles, for example if the pinctrl driver has not yet
registered. Thus make sure that the error path in your driver gracefully
cleans up and is ready to retry the probing later in the startup process.

pinctrl과 GPIO를 함께 쓰는 driver의 획득 순서

같은 device가 pinctrl state와 GPIO descriptor를 모두 필요로 하면 먼저 pinctrl handle을 얻고 적절한 state를 선택한 뒤 `gpiod_get()` 또는 managed GPIO 요청을 수행해야 합니다. 그래야 GPIO를 구동하기 전에 pull, drive, mux가 안전한 전기 상태에 놓입니다.

GPIO operation이 내부적으로 pinctrl backend를 호출할 수 있으므로 consumer는 이 연결을 직접 재현하지 말고 gpiod API를 사용합니다. 같은 pin과 mux hardware를 공유한다면 GPIO driver는 반드시 pinctrl backend와 협력해야 합니다.

예외는 GPIO block이 pinctrl 설정을 완전히 override하고 독립적으로 안전한 상태를 만들 수 있는 하드웨어입니다. 그렇지 않다면 GPIO와 pinctrl을 분리된 controller처럼 구현하면 ownership과 electrical state가 어긋납니다.

Drivers needing both pin control and GPIOs
==========================================

Again, it is discouraged to let drivers lookup and select pin control states
themselves, but again sometimes this is unavoidable.

So say that your driver is fetching its resources like this:

.. code-block:: c

        #include <linux/pinctrl/consumer.h>
        #include <linux/gpio/consumer.h>

        struct pinctrl *pinctrl;
        struct gpio_desc *gpio;

        pinctrl = devm_pinctrl_get_select_default(&dev);
        gpio = devm_gpiod_get(&dev, "foo");

Here we first request a certain pin state and then request GPIO "foo" to be
used. If you're using the subsystems orthogonally like this, you should
nominally always get your pinctrl handle and select the desired pinctrl
state BEFORE requesting the GPIO. This is a semantic convention to avoid
situations that can be electrically unpleasant, you will certainly want to
mux in and bias pins in a certain way before the GPIO subsystems starts to
deal with them.

The above can be hidden: using the device core, the pinctrl core may be
setting up the config and muxing for the pins right before the device is
probing, nevertheless orthogonal to the GPIO subsystem.

But there are also situations where it makes sense for the GPIO subsystem
to communicate directly with the pinctrl subsystem, using the latter as a
back-end. This is when the GPIO driver may call out to the functions
described in the section `Pin control interaction with the GPIO subsystem`_
above. This only involves per-pin multiplexing, and will be completely
hidden behind the gpiod_*() function namespace. In this case, the driver
need not interact with the pin control subsystem at all.

If a pin control driver and a GPIO driver is dealing with the same pins
and the use cases involve multiplexing, you MUST implement the pin controller
as a back-end for the GPIO driver like this, unless your hardware design
is such that the GPIO controller can override the pin controller's
multiplexing state through hardware without the need to interact with the
pin control system.

controller 자체의 pin hogging

pin hog는 특정 pinmux 또는 configuration을 controller 등록 직후 항상 적용해야 할 때 사용합니다. 이 경우 pinctrl consumer와 pin controller가 같은 device이며 default state가 controller 자신의 고정 설정을 담습니다.

core는 pinctrl device 등록 뒤 즉시 해당 controller에 대해 get, lookup, select 순서를 수행하므로 다른 consumer가 pin을 요청하기 전에 hog state가 예약됩니다. board mapping에서는 `PIN_MAP_MUX_GROUP_HOG_DEFAULT()`로 default mux hog를 기술할 수 있습니다.

System pin control hogging
==========================

Pin control map entries can be hogged by the core when the pin controller
is registered. This means that the core will attempt to call ``pinctrl_get()``,
``pinctrl_lookup_state()`` and ``pinctrl_select_state()`` on it immediately after
the pin control device has been registered.

This occurs for mapping table entries where the client device name is equal
to the pin controller device name, and the state name is ``PINCTRL_STATE_DEFAULT``:

.. code-block:: c

        {
                .dev_name = "pinctrl-foo",
                .name = PINCTRL_STATE_DEFAULT,
                .type = PIN_MAP_TYPE_MUX_GROUP,
                .ctrl_dev_name = "pinctrl-foo",
                .function = "power_func",
        },

Since it may be common to request the core to hog a few always-applicable
mux settings on the primary pin controller, there is a convenience macro for
this:

.. code-block:: c

        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */,
                                      "power_func")

This gives the exact same result as the above construction.

runtime pinmux 전환과 debugfs 검사

device가 runtime에 물리 위치를 바꿔야 하면 `spi0-pos-A`, `spi0-pos-B` 같은 state를 probe 때 미리 lookup하고 process context에서 `pinctrl_select_state()`로 전환합니다. state를 선택하는 순간 새 group이 예약되고 이전 state의 pin은 해제되므로 같은 pin을 시간에 따라 서로 다른 function에 사용할 수 있습니다.

전환은 register I/O와 locking을 포함할 수 있으므로 interrupt context에서 수행하지 않습니다. 대체 state가 실제로 충돌 없이 구성되는지, 전환 중 device traffic이 멈추었는지 driver가 보장해야 합니다.

debugfs의 `/sys/kernel/debug/pinctrl` root에는 `pinctrl-devices`, `pinctrl-handles`, `pinctrl-maps`가 있어 등록된 controller, consumer handle, mapping을 확인할 수 있습니다. 각 controller directory에는 `pins`, `gpio-ranges`, `pingroups`, `pinconf-pins`, `pinconf-groups`, `pinmux-functions`, `pinmux-pins`, `pinmux-select`가 나타납니다.

디버깅 목적으로 `echo "<group-name function-name>" > pinmux-select`를 써서 특정 group/function 조합을 선택할 수 있습니다. 이는 상태를 강제로 바꾸는 저수준 인터페이스이므로 production 제어 경로가 아니라 controller와 mapping 검증에 사용해야 합니다.

Runtime pinmuxing
=================

It is possible to mux a certain function in and out at runtime, say to move
an SPI port from one set of pins to another set of pins. Say for example for
spi0 in the example above, we expose two different groups of pins for the same
function, but with different named in the mapping as described under
"Advanced mapping" above. So that for an SPI device, we have two states named
"pos-A" and "pos-B".

This snippet first initializes a state object for both groups (in foo_probe()),
then muxes the function in the pins defined by group A, and finally muxes it in
on the pins defined by group B:

.. code-block:: c

        #include <linux/pinctrl/consumer.h>

        struct pinctrl *p;
        struct pinctrl_state *s1, *s2;

        foo_probe()
        {
                /* Setup */
                p = devm_pinctrl_get(&device);
                if (IS_ERR(p))
                        ...

                s1 = pinctrl_lookup_state(p, "pos-A");
                if (IS_ERR(s1))
                        ...

                s2 = pinctrl_lookup_state(p, "pos-B");
                if (IS_ERR(s2))
                        ...
        }

        foo_switch()
        {
                /* Enable on position A */
                ret = pinctrl_select_state(p, s1);
                if (ret < 0)
                        ...

                ...

                /* Enable on position B */
                ret = pinctrl_select_state(p, s2);
                if (ret < 0)
                        ...

                ...
        }

The above has to be done from process context. The reservation of the pins
will be done when the state is activated, so in effect one specific pin
can be used by different functions at different times on a running system.


Debugfs files
=============

These files are created in ``/sys/kernel/debug/pinctrl``:

- ``pinctrl-devices``: prints each pin controller device along with columns to
  indicate support for pinmux and pinconf

- ``pinctrl-handles``: prints each configured pin controller handle and the
  corresponding pinmux maps

- ``pinctrl-maps``: prints all pinctrl maps

A sub-directory is created inside of ``/sys/kernel/debug/pinctrl`` for each pin
controller device containing these files:

- ``pins``: prints a line for each pin registered on the pin controller. The
  pinctrl driver may add additional information such as register contents.

- ``gpio-ranges``: prints ranges that map gpio lines to pins on the controller

- ``pingroups``: prints all pin groups registered on the pin controller

- ``pinconf-pins``: prints pin config settings for each pin

- ``pinconf-groups``: prints pin config settings per pin group

- ``pinmux-functions``: prints each pin function along with the pin groups that
  map to the pin function

- ``pinmux-pins``: iterates through all pins and prints mux owner, gpio owner
  and if the pin is a hog

- ``pinmux-select``: write to this file to activate a pin function for a group:

  .. code-block:: sh

        echo "<group-name function-name>" > pinmux-select