Legacy Qualcomm SuperSpeed DWC3 Controller

Legacy Qualcomm SuperSpeed DWC3 wrapper

GPL-2.0 또는 BSD-2-Clause로 배포되는 이 schema는 legacy Qualcomm SuperSpeed DWC3 USB SoC controller를 정의합니다. 관리자는 Wesley Cheng입니다.

이 binding은 폐기되었으며 새 설계에서는 결합형 `qcom,snps-dwc3` binding을 사용해야 합니다. 선택 조건은 `compatible` 배열에 `qcom,dwc3`가 포함된 node입니다.

45개 SoC variant와 fallback

`compatible`은 IPQ, MSM, QCM, QCS, QDU, SA, SAR, SC, SDM, SDX, SM, X1E 계열의 열거된 45개 SoC-specific 문자열 중 하나를 첫 항목으로 사용하고, 둘째 항목은 항상 `qcom,dwc3`입니다. `-mp` suffix variant는 multi-port wrapper를 뜻합니다.

properties:
  compatible:
    items:
      - enum:
          - qcom,ipq4019-dwc3
          - qcom,ipq5018-dwc3
          - qcom,ipq5332-dwc3
          - qcom,ipq5424-dwc3
          - qcom,ipq6018-dwc3
          - qcom,ipq8064-dwc3
          - qcom,ipq8074-dwc3
          - qcom,ipq9574-dwc3
          - qcom,msm8953-dwc3
          - qcom,msm8994-dwc3
          - qcom,msm8996-dwc3
          - qcom,msm8998-dwc3
          - qcom,qcm2290-dwc3
          - qcom,qcs404-dwc3
          - qcom,qcs615-dwc3
          - qcom,qcs8300-dwc3
          - qcom,qdu1000-dwc3
          - qcom,sa8775p-dwc3
          - qcom,sar2130p-dwc3
          - qcom,sc7180-dwc3
          - qcom,sc7280-dwc3
          - qcom,sc8180x-dwc3
          - qcom,sc8180x-dwc3-mp
          - qcom,sc8280xp-dwc3
          - qcom,sc8280xp-dwc3-mp
          - qcom,sdm660-dwc3
          - qcom,sdm670-dwc3
          - qcom,sdm845-dwc3
          - qcom,sdx55-dwc3
          - qcom,sdx65-dwc3
          - qcom,sdx75-dwc3
          - qcom,sm4250-dwc3
          - qcom,sm6115-dwc3
          - qcom,sm6125-dwc3
          - qcom,sm6350-dwc3
          - qcom,sm6375-dwc3
          - qcom,sm8150-dwc3
          - qcom,sm8250-dwc3
          - qcom,sm8350-dwc3
          - qcom,sm8450-dwc3
          - qcom,sm8550-dwc3
          - qcom,sm8650-dwc3
          - qcom,sm8750-dwc3
          - qcom,x1e80100-dwc3
          - qcom,x1e80100-dwc3-mp
      - const: qcom,dwc3

QSCRATCH, clock와 interconnect

`reg`는 QSCRATCH wrapper register set의 offset과 길이 한 쌍입니다. address cell과 size cell은 각각 1 또는 2이고 `ranges`를 지원합니다. power domain과 required OPP는 각각 하나입니다.

variant에 따라 clock 1~9개를 사용합니다. 대표 이름은 System Config NOC `cfg_noc`, SS에서 최소 125 MHz·HS에서 최소 60 MHz인 master/core `core`, system bus AXI `iface`, U3 low-power wakeup용 `sleep`, host ITP/SOF 생성을 위한 19.2 MHz `mock_utmi`입니다.

reset은 하나입니다. interconnect는 최대 두 개이고 이름은 DDR 경로 `usb-ddr`, application 경로 `apps-usb` 순서입니다.

reg:
  description: Offset and length of register set for QSCRATCH wrapper
  maxItems: 1

"#address-cells":
  enum: [ 1, 2 ]

"#size-cells":
  enum: [ 1, 2 ]

ranges: true

power-domains:
  description: specifies a phandle to PM domain provider node
  maxItems: 1

required-opps:
  maxItems: 1

clocks:
  description: |
    Several clocks are used, depending on the variant. Typical ones are::
     - cfg_noc:: System Config NOC clock.
     - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
              60MHz for HS operation.
     - iface:: System bus AXI clock.
     - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
               power mode (U3).
     - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
                   mode. Its frequency should be 19.2MHz.
  minItems: 1
  maxItems: 9

clock-names:
  minItems: 1
  maxItems: 9

resets:
  maxItems: 1

interconnects:
  maxItems: 2

interconnect-names:
  items:
    - const: usb-ddr
    - const: apps-usb

PHY wakeup interrupt와 child DWC3

interrupt는 2~18개입니다. `pwr_event`는 기타 power event wakeup, `hs_phy_irq`는 DP/DM 또는 QUSB2 interrupt와 상호 배타적인 HS PHY interrupt입니다.

QUSB2 PHY SoC는 별도 DP/DM IRQ 대신 `qusb2_phy` 하나를 사용하며 PHY address space의 `QUSB2PHY_INTR_CTRL` register에서 DPSE/DMSE 동작을 구성합니다. `dp_hs_phy_irq`와 `dm_hs_phy_irq`는 SoC DP/DM pad 변화를 직접 반영하고 비-QUSB2 target의 wakeup에 쓰이지만 SDM670, SDM845, SM6350은 예외입니다. `ss_phy_irq`는 SuperSpeed remote wakeup용입니다.

`qcom,select-utmi-as-pipe-clk`가 있으면 SSPHY 없이 HS/FS/LS mode만 지원할 때 USB3 `pipe_clk` 요구를 끕니다. wrapper는 wakeup source가 될 수 있습니다. 필수 child `usb@주소`는 `snps,dwc3.yaml`을 따르며 child 자체의 `wakeup-source`는 금지됩니다.

  interrupts:
    description: |
      Different types of interrupts are used based on HS PHY used on target:
        - pwr_event: Used for wakeup based on other power events.
        - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
                       hs_phy_irq which is not triggered by default and its
                       functionality is mutually exclusive to that of
                       {dp/dm}_hs_phy_irq and qusb2_phy_irq.
        - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
                      expose only a single IRQ whose behavior can be modified
                      by the QUSB2PHY_INTR_CTRL register. The required DPSE/
                      DMSE configuration is done in QUSB2PHY_INTR_CTRL register
                      of PHY address space.
        - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
                               DM pads of the SoC. These are used for wakeup
                               only on SoCs with non-QUSB2 targets with
                               exception of SDM670/SDM845/SM6350.
        - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
    minItems: 2
    maxItems: 18

  interrupt-names:
    minItems: 2
    maxItems: 18

  qcom,select-utmi-as-pipe-clk:
    description:
      If present, disable USB3 pipe_clk requirement.
      Used when dwc3 operates without SSPHY and only
      HS/FS/LS modes are supported.
    type: boolean

  wakeup-source: true

# Required child node:

patternProperties:
  "^usb@[0-9a-f]+$":
    $ref: snps,dwc3.yaml#
    unevaluatedProperties: false

    properties:
      wakeup-source: false

아홉 필수 wrapper 속성

필수 속성은 `compatible`, `reg`, `#address-cells`, `#size-cells`, `ranges`, `clocks`, `clock-names`, `interrupts`, `interrupt-names`의 아홉 개입니다. 이후 `allOf`는 compatible별 clock과 interrupt 배열을 제한합니다.

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - clocks
  - clock-names
  - interrupts
  - interrupt-names

allOf:

IPQ4019·5332·8064 clock

IPQ4019과 IPQ5332는 최대 세 clock을 `core`, `sleep`, `mock_utmi` 순서로 사용합니다. IPQ8064는 `core` clock 하나만 사용하며 SS 동작에는 최소 125 MHz, HS 동작에는 최소 60 MHz가 필요합니다.

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,ipq4019-dwc3
            - qcom,ipq5332-dwc3
  then:
    properties:
      clocks:
        maxItems: 3
      clock-names:
        items:
          - const: core
          - const: sleep
          - const: mock_utmi

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,ipq8064-dwc3
  then:
    properties:
      clocks:
        items:
          - description: Master/Core clock, has to be >= 125 MHz
              for SS operation and >= 60MHz for HS operation.
      clock-names:
        items:
          - const: core

5-clock 계열과 IPQ6018

IPQ9574, MSM8953/8996/8998, QCS8300, SA8775P, SC7180/7280, SDM670/845, SDX55/65/75, SM6350은 최대 다섯 clock을 `cfg_noc`, `core`, `iface`, `sleep`, `mock_utmi` 순서로 사용합니다.

IPQ6018은 3~4개 clock을 사용합니다. 세 항목 구성은 `core`, `sleep`, `mock_utmi`이고 네 항목 구성은 맨 앞에 `cfg_noc`을 추가합니다.

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,ipq9574-dwc3
            - qcom,msm8953-dwc3
            - qcom,msm8996-dwc3
            - qcom,msm8998-dwc3
            - qcom,qcs8300-dwc3
            - qcom,sa8775p-dwc3
            - qcom,sc7180-dwc3
            - qcom,sc7280-dwc3
            - qcom,sdm670-dwc3
            - qcom,sdm845-dwc3
            - qcom,sdx55-dwc3
            - qcom,sdx65-dwc3
            - qcom,sdx75-dwc3
            - qcom,sm6350-dwc3
  then:
    properties:
      clocks:
        maxItems: 5
      clock-names:
        items:
          - const: cfg_noc
          - const: core
          - const: iface
          - const: sleep
          - const: mock_utmi

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,ipq6018-dwc3
  then:
    properties:
      clocks:
        minItems: 3
        maxItems: 4
      clock-names:
        oneOf:
          - items:
              - const: core
              - const: sleep
              - const: mock_utmi
          - items:
              - const: cfg_noc
              - const: core
              - const: sleep
              - const: mock_utmi

두 종류 4-clock 배열

IPQ8074와 QDU1000은 최대 네 clock을 `cfg_noc`, `core`, `sleep`, `mock_utmi` 순서로 사용합니다.

IPQ5018, MSM8994, QCS404도 최대 네 개지만 순서는 `core`, `iface`, `sleep`, `mock_utmi`이며 `cfg_noc` 대신 `iface`가 포함됩니다.

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,ipq8074-dwc3
            - qcom,qdu1000-dwc3
  then:
    properties:
      clocks:
        maxItems: 4
      clock-names:
        items:
          - const: cfg_noc
          - const: core
          - const: sleep
          - const: mock_utmi

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,ipq5018-dwc3
            - qcom,msm8994-dwc3
            - qcom,qcs404-dwc3
  then:
    properties:
      clocks:
        maxItems: 4
      clock-names:
        items:
          - const: core
          - const: iface
          - const: sleep
          - const: mock_utmi

9-clock NOC와 SDM660

SC8280XP·X1E80100의 single-port 및 multi-port variant는 최대 아홉 clock을 사용합니다. 순서는 `cfg_noc`, `core`, `iface`, `sleep`, `mock_utmi`, `noc_aggr`, `noc_aggr_north`, `noc_aggr_south`, `noc_sys`입니다.

SDM660은 4~5개 clock을 사용합니다. 다섯 항목은 `cfg_noc`, `core`, `iface`, `sleep`, `mock_utmi`이고 네 항목은 여기서 `iface`를 뺀 배열입니다.

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,sc8280xp-dwc3
            - qcom,sc8280xp-dwc3-mp
            - qcom,x1e80100-dwc3
            - qcom,x1e80100-dwc3-mp
  then:
    properties:
      clocks:
        maxItems: 9
      clock-names:
        items:
          - const: cfg_noc
          - const: core
          - const: iface
          - const: sleep
          - const: mock_utmi
          - const: noc_aggr
          - const: noc_aggr_north
          - const: noc_aggr_south
          - const: noc_sys

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,sdm660-dwc3
  then:
    properties:
      clocks:
        minItems: 4
        maxItems: 5
      clock-names:
        oneOf:
          - items:
              - const: cfg_noc
              - const: core
              - const: iface
              - const: sleep
              - const: mock_utmi
          - items:
              - const: cfg_noc
              - const: core
              - const: sleep
              - const: mock_utmi

XO clock 계열과 SM8350

QCM2290, QCS615, SAR2130P, SC8180X single/multi-port, SM6115/6125/8150/8250/8450/8550/8650/8750은 최소 여섯 clock을 사용하며 기본 순서는 `cfg_noc`, `core`, `iface`, `sleep`, `mock_utmi`, `xo`입니다.

SM8350은 5~6개 clock과 최소 다섯 clock-name을 사용합니다. 첫 다섯 이름은 `cfg_noc`, `core`, `iface`, `sleep`, `mock_utmi`이며 여섯째 `xo`는 선택적입니다.

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,qcm2290-dwc3
            - qcom,qcs615-dwc3
            - qcom,sar2130p-dwc3
            - qcom,sc8180x-dwc3
            - qcom,sc8180x-dwc3-mp
            - qcom,sm6115-dwc3
            - qcom,sm6125-dwc3
            - qcom,sm8150-dwc3
            - qcom,sm8250-dwc3
            - qcom,sm8450-dwc3
            - qcom,sm8550-dwc3
            - qcom,sm8650-dwc3
            - qcom,sm8750-dwc3
  then:
    properties:
      clocks:
        minItems: 6
      clock-names:
        items:
          - const: cfg_noc
          - const: core
          - const: iface
          - const: sleep
          - const: mock_utmi
          - const: xo

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,sm8350-dwc3
  then:
    properties:
      clocks:
        minItems: 5
        maxItems: 6
      clock-names:
        minItems: 5
        items:
          - const: cfg_noc
          - const: core
          - const: iface
          - const: sleep
          - const: mock_utmi
          - const: xo

QUSB2 interrupt 배열

IPQ5018/6018/8074, MSM8953/8998은 2~3개 interrupt를 `pwr_event`, `qusb2_phy`, 선택 `ss_phy_irq` 순서로 사용합니다.

MSM8996, QCS404, SDM660, SM6115/6125는 3~4개 interrupt를 `pwr_event`, `qusb2_phy`, `hs_phy_irq`, 선택 `ss_phy_irq` 순서로 사용합니다.

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,ipq5018-dwc3
            - qcom,ipq6018-dwc3
            - qcom,ipq8074-dwc3
            - qcom,msm8953-dwc3
            - qcom,msm8998-dwc3
  then:
    properties:
      interrupts:
        minItems: 2
        maxItems: 3
      interrupt-names:
        minItems: 2
        items:
          - const: pwr_event
          - const: qusb2_phy
          - const: ss_phy_irq

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,msm8996-dwc3
            - qcom,qcs404-dwc3
            - qcom,sdm660-dwc3
            - qcom,sm6115-dwc3
            - qcom,sm6125-dwc3
  then:
    properties:
      interrupts:
        minItems: 3
        maxItems: 4
      interrupt-names:
        minItems: 3
        items:
          - const: pwr_event
          - const: qusb2_phy
          - const: hs_phy_irq
          - const: ss_phy_irq

DP/DM interrupt 배열

IPQ5332는 최대 세 interrupt를 `pwr_event`, `dp_hs_phy_irq`, `dm_hs_phy_irq` 순서로 사용합니다.

single-port X1E80100은 3~4개 interrupt를 `pwr_event`, `dp_hs_phy_irq`, `dm_hs_phy_irq`, 선택 `ss_phy_irq` 순서로 사용합니다.

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,ipq5332-dwc3
  then:
    properties:
      interrupts:
        maxItems: 3
      interrupt-names:
        items:
          - const: pwr_event
          - const: dp_hs_phy_irq
          - const: dm_hs_phy_irq

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,x1e80100-dwc3
  then:
    properties:
      interrupts:
        minItems: 3
        maxItems: 4
      interrupt-names:
        minItems: 3
        items:
          - const: pwr_event
          - const: dp_hs_phy_irq
          - const: dm_hs_phy_irq
          - const: ss_phy_irq

4~5개 wakeup interrupt 계열

열거된 IPQ4019/8064, MSM8994, QCS615/8300, QDU1000, SA8775P, SC7180/7280/8180X/8280XP, SDM670/845, SDX55/65/75, SM4250/6350/8150/8250/8350/8450/8550/8650/8750은 4~5개 interrupt를 사용합니다.

이름은 `pwr_event`, `hs_phy_irq`, `dp_hs_phy_irq`, `dm_hs_phy_irq`, 선택 `ss_phy_irq` 순서입니다.

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,ipq4019-dwc3
            - qcom,ipq8064-dwc3
            - qcom,msm8994-dwc3
            - qcom,qcs615-dwc3
            - qcom,qcs8300-dwc3
            - qcom,qdu1000-dwc3
            - qcom,sa8775p-dwc3
            - qcom,sc7180-dwc3
            - qcom,sc7280-dwc3
            - qcom,sc8180x-dwc3
            - qcom,sc8280xp-dwc3
            - qcom,sdm670-dwc3
            - qcom,sdm845-dwc3
            - qcom,sdx55-dwc3
            - qcom,sdx65-dwc3
            - qcom,sdx75-dwc3
            - qcom,sm4250-dwc3
            - qcom,sm6350-dwc3
            - qcom,sm8150-dwc3
            - qcom,sm8250-dwc3
            - qcom,sm8350-dwc3
            - qcom,sm8450-dwc3
            - qcom,sm8550-dwc3
            - qcom,sm8650-dwc3
            - qcom,sm8750-dwc3
  then:
    properties:
      interrupts:
        minItems: 4
        maxItems: 5
      interrupt-names:
        minItems: 4
        items:
          - const: pwr_event
          - const: hs_phy_irq
          - const: dp_hs_phy_irq
          - const: dm_hs_phy_irq
          - const: ss_phy_irq

Multi-port 10개·18개 interrupt

SC8180X-MP와 X1E80100-MP는 정확히 10개 interrupt를 사용합니다. 두 port의 `pwr_event`, `hs_phy`, 각 port의 DP/DM pair, 두 `ss_phy` 순서입니다.

SC8280XP-MP는 정확히 18개입니다. port 1~4의 `pwr_event`, `hs_phy`, DP/DM pair 8개, 마지막으로 `ss_phy_1`, `ss_phy_2` 순서입니다.

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,sc8180x-dwc3-mp
            - qcom,x1e80100-dwc3-mp
  then:
    properties:
      interrupts:
        minItems: 10
        maxItems: 10
      interrupt-names:
        items:
          - const: pwr_event_1
          - const: pwr_event_2
          - const: hs_phy_1
          - const: hs_phy_2
          - const: dp_hs_phy_1
          - const: dm_hs_phy_1
          - const: dp_hs_phy_2
          - const: dm_hs_phy_2
          - const: ss_phy_1
          - const: ss_phy_2

- if:
    properties:
      compatible:
        contains:
          enum:
            - qcom,sc8280xp-dwc3-mp
  then:
    properties:
      interrupts:
        minItems: 18
        maxItems: 18
      interrupt-names:
        items:
          - const: pwr_event_1
          - const: pwr_event_2
          - const: pwr_event_3
          - const: pwr_event_4
          - const: hs_phy_1
          - const: hs_phy_2
          - const: hs_phy_3
          - const: hs_phy_4
          - const: dp_hs_phy_1
          - const: dm_hs_phy_1
          - const: dp_hs_phy_2
          - const: dm_hs_phy_2
          - const: dp_hs_phy_3
          - const: dm_hs_phy_3
          - const: dp_hs_phy_4
          - const: dm_hs_phy_4
          - const: ss_phy_1
          - const: ss_phy_2

SDM845 QSCRATCH와 DWC3 core

정의되지 않은 추가 속성은 허용하지 않습니다. 예제 SDM845 `usb@a6f8800` wrapper는 0x400-byte QSCRATCH register, 2-cell child 주소·크기, 다섯 clock을 사용합니다. mock UTMI는 19.2 MHz, master는 150 MHz로 할당합니다.

interrupt는 GIC SPI 130 `pwr_event`, 131 `hs_phy_irq`, 489 `dp_hs_phy_irq`, 488 `dm_hs_phy_irq`, 486 `ss_phy_irq` 순서입니다. USB30 primary power domain과 block reset을 연결합니다.

child `usb@a600000`은 `snps,dwc3`, 0xcd00-byte 영역, GIC SPI 133, Apps SMMU stream 0x740을 사용합니다. U2 suspend PHY와 LPM quirk를 끄고 USB2·USB3 PHY를 `usb2-phy`, `usb3-phy` 이름으로 연결합니다.

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        usb@a6f8800 {
            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
            reg = <0 0x0a6f8800 0 0x400>;

            #address-cells = <2>;
            #size-cells = <2>;
            ranges;
            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
            clock-names = "cfg_noc",
                          "core",
                          "iface",
                          "sleep",
                          "mock_utmi";

            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
            assigned-clock-rates = <19200000>, <150000000>;

            interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
                         <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "pwr_event", "hs_phy_irq",
                          "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";

            power-domains = <&gcc USB30_PRIM_GDSC>;

            resets = <&gcc GCC_USB30_PRIM_BCR>;

            usb@a600000 {
                compatible = "snps,dwc3";
                reg = <0 0x0a600000 0 0xcd00>;
                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
                iommus = <&apps_smmu 0x740 0>;
                snps,dis_u2_susphy_quirk;
                snps,dis_enblslpm_quirk;
                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
                phy-names = "usb2-phy", "usb3-phy";
            };
        };
    };