NVIDIA Tegra234 xHCI Controller

NVIDIA Tegra234 xHCI

GPL-2.0-only 또는 BSD-2-Clause로 배포되는 이 schema는 NVIDIA Tegra234 xHCI controller를 정의합니다. controller는 최대 여덟 port를 제어하며 USB 2.0 port 네 개와 USB 3.2 Gen1 x1 port 네 개로 구성됩니다. 관리자는 Thierry Reding과 Jon Hunter입니다.

HCD·FPCI·BAR2와 interrupt

`compatible`은 `nvidia,tegra234-xusb`입니다. register는 xHCI host `hcd`, XUSB FPCI `fpci`, XUSB BAR2 `bar2` 순서의 세 개입니다. interrupt는 xHCI host와 mailbox 순서의 두 개입니다.

properties:
  compatible:
    const: nvidia,tegra234-xusb

  reg:
    items:
      - description: xHCI host registers
      - description: XUSB FPCI registers
      - description: XUSB bar2 registers

  reg-names:
    items:
      - const: hcd
      - const: fpci
      - const: bar2

  interrupts:
    items:
      - description: xHCI host interrupt
      - description: mailbox interrupt

아홉 clock, interconnect와 IOMMU

clock은 XUSB host, Falcon source, SuperSpeed, SuperSpeed source, High-Speed source, Full-Speed source, USB PLL, reference, I/O PLL 순서이며 이름은 `xusb_host`, `xusb_falcon_src`, `xusb_ss`, `xusb_ss_src`, `xusb_hs_src`, `xusb_fs_src`, `pll_u_480m`, `clk_m`, `pll_e`입니다.

memory interconnect는 read `dma-mem`과 `write` client 두 개이고 IOMMU는 하나만 허용합니다.

clocks:
  items:
    - description: XUSB host clock
    - description: XUSB Falcon source clock
    - description: XUSB SuperSpeed clock
    - description: XUSB SuperSpeed source clock
    - description: XUSB HighSpeed clock source
    - description: XUSB FullSpeed clock source
    - description: USB PLL
    - description: reference clock
    - description: I/O PLL

clock-names:
  items:
    - const: xusb_host
    - const: xusb_falcon_src
    - const: xusb_ss
    - const: xusb_ss_src
    - const: xusb_hs_src
    - const: xusb_fs_src
    - const: pll_u_480m
    - const: clk_m
    - const: pll_e

interconnects:
  items:
    - description: read client
    - description: write client

interconnect-names:
  items:
    - const: dma-mem # read
    - const: write

iommus:
  maxItems: 1

여덟 PHY, power domain과 coherent DMA

XUSB pad controller phandle을 사용합니다. PHY와 이름은 1~8개이며 USB2 port 0~3과 USB3 port 0~3을 허용합니다.

power domain은 Host·USB2용 XUSBC `xusb_host`와 SuperSpeed용 XUSBA `xusb_ss`입니다. `dma-coherent` 속성을 지원합니다.

nvidia,xusb-padctl:
  $ref: /schemas/types.yaml#/definitions/phandle
  description: phandle to the XUSB pad controller that is used to configure
    the USB pads used by the XHCI controller

phys:
  minItems: 1
  maxItems: 8

phy-names:
  minItems: 1
  maxItems: 8
  items:
    enum:
      - usb2-0
      - usb2-1
      - usb2-2
      - usb2-3
      - usb3-0
      - usb3-1
      - usb3-2
      - usb3-3

power-domains:
  items:
    - description: XUSBC power domain (for Host and USB 2.0)
    - description: XUSBA power domain (for SuperSpeed)

power-domain-names:
  items:
    - const: xusb_host
    - const: xusb_ss

dma-coherent: true

공통 xHCI schema

공통 `usb-xhci.yaml`을 상속하며 평가되지 않은 추가 속성을 허용하지 않습니다.

allOf:
  - $ref: usb-xhci.yaml

unevaluatedProperties: false

Tegra234 BPMP XUSB 예제

예제 `usb@3610000`은 `hcd`, `fpci`, `bar2` register와 level-high GIC SPI 163·164, BPMP clock 아홉 개를 사용합니다.

host read·write interconnect, `smmu_niso1`의 XUSB host stream ID, XUSBC·XUSBA power domain과 pad controller를 연결하며 예제 PHY는 `usb2-0` 하나입니다.

examples:
  - |
    #include <dt-bindings/clock/tegra234-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra234-mc.h>
    #include <dt-bindings/power/tegra234-powergate.h>

    usb@3610000 {
        compatible = "nvidia,tegra234-xusb";
        reg = <0x03610000 0x40000>,
              <0x03600000 0x10000>,
              <0x03650000 0x10000>;
        reg-names = "hcd", "fpci", "bar2";

        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
                 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
                 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
                 <&bpmp TEGRA234_CLK_XUSB_SS>,
                 <&bpmp TEGRA234_CLK_CLK_M>,
                 <&bpmp TEGRA234_CLK_XUSB_FS>,
                 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
                 <&bpmp TEGRA234_CLK_CLK_M>,
                 <&bpmp TEGRA234_CLK_PLLE>;
        clock-names = "xusb_host", "xusb_falcon_src",
                      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
                      "xusb_fs_src", "pll_u_480m", "clk_m",
                      "pll_e";
        interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>,
                        <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>;
        interconnect-names = "dma-mem", "write";
        iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>;

        power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
                        <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
        power-domain-names = "xusb_host", "xusb_ss";

        nvidia,xusb-padctl = <&xusb_padctl>;

        phys = <&pad_lanes_usb2_0>;
        phy-names = "usb2-0";
    };