NXP i.MX8MP SoC USB Controller

NXP i.MX8MP SoC USB controller

GPL-2.0-only 또는 BSD-2-Clause로 배포되는 이 schema는 NXP i.MX8MP SoC USB controller를 정의합니다. 저작권자는 NXP, 관리자는 Li Jun입니다.

Compatible, register와 wakeup interrupt

`compatible`은 `fsl,imx8mp-dwc3` 단독이거나 `fsl,imx95-dwc3` 뒤에 i.MX8MP fallback을 둔 조합입니다.

`reg`의 첫 영역은 HSIO Block Control register set, 둘째 영역은 SoC의 DWC3 core wrapper register set입니다. address cell과 size cell 수는 각각 1 또는 2입니다.

`dma-ranges`는 Devicetree Specification 2.3.9절을 따르고 `ranges`를 허용합니다. interrupt는 wakeup event 수신 시 assert되는 항목 하나입니다.

properties:
  compatible:
    oneOf:
      - items:
          - const: fsl,imx95-dwc3
          - const: fsl,imx8mp-dwc3
      - const: fsl,imx8mp-dwc3

  reg:
    items:
      - description: Address and length of the register set for HSIO Block Control
      - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  dma-ranges:
    description:
      See section 2.3.9 of the DeviceTree Specification.

  ranges: true

  interrupts:
    maxItems: 1
    description: The interrupt that is asserted when a wakeup event is
      received.

Clock, platform boolean과 power domain

clock은 두 개입니다. `hsio`는 system HSIO root clock이고 `suspend`는 USB wakeup logic에 사용하는 suspend clock입니다.

`fsl,permanently-attached`는 downstream port의 device가 영구 연결됐음을 나타냅니다. `fsl,disable-port-power-control`은 host controller가 port power control을 포함하는지 나타내며 capability register HCCPARAMS의 bit 3을 정의합니다.

`fsl,over-current-active-low`는 over-current signal이 active-low임을, `fsl,power-active-low`는 power pad PWR polarity가 active-low임을 뜻합니다. power domain은 최대 하나입니다.

clocks:
  description:
    A list of phandle and clock-specifier pairs for the clocks
    listed in clock-names.
  items:
    - description: system hsio root clock.
    - description: suspend clock, used for usb wakeup logic.

clock-names:
  items:
    - const: hsio
    - const: suspend

fsl,permanently-attached:
  type: boolean
  description:
    Indicates if the device attached to a downstream port is
    permanently attached.

fsl,disable-port-power-control:
  type: boolean
  description:
    Indicates whether the host controller implementation includes port
    power control. Defines Bit 3 in capability register (HCCPARAMS).

fsl,over-current-active-low:
  type: boolean
  description:
    Over current signal polarity is active low.

fsl,power-active-low:
  type: boolean
  description:
    Power pad (PWR) polarity is active low.

power-domains:
  maxItems: 1

DWC3 child, 필수 속성과 조건

16진 주소를 이름에 넣은 `usb@...` child node는 `snps,dwc3.yaml`을 따라야 합니다.

필수 속성은 `compatible`, `reg`, `#address-cells`, `#size-cells`, `ranges`, `clocks`, `clock-names`, `interrupts`, `power-domains`입니다.

`compatible`이 `fsl,imx8mp-dwc3`이면 `dma-ranges`도 반드시 필요합니다. 정의되지 않은 추가 속성은 허용하지 않습니다.

# Required child node:

patternProperties:
  "^usb@[0-9a-f]+$":
    $ref: snps,dwc3.yaml#

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - clocks
  - clock-names
  - interrupts
  - power-domains

allOf:
  - if:
      properties:
        compatible:
          const: fsl,imx8mp-dwc3
    then:
      required:
        - dma-ranges

additionalProperties: false

i.MX8MP wrapper와 DWC3 core 예제

예제 wrapper `usb@32f10100`은 HSIO control과 DWC3 wrapper 두 register 영역, HSIO root·USB root clock, GIC SPI 148 wakeup interrupt, USB power domain, `dma-ranges`와 빈 `ranges`를 사용합니다.

child `usb@38100000`은 `snps,dwc3`, 0x10000-byte register 영역, `bus_early`·`ref`·`suspend` clock을 지정합니다. HSIO AXI clock parent를 SYS PLL2 500M으로 정하고 rate를 500 MHz로 설정합니다.

DWC3 core interrupt는 GIC SPI 40입니다. 같은 `usb3_phy0`를 USB2·USB3 PHY로 참조하고 `snps,dis-u2-freeclk-exists-quirk`를 활성화합니다.

examples:
  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/power/imx8mp-power.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    usb3_0: usb@32f10100 {
      compatible = "fsl,imx8mp-dwc3";
      reg = <0x32f10100 0x8>,
            <0x381f0000 0x20>;
      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
               <&clk IMX8MP_CLK_USB_ROOT>;
      clock-names = "hsio", "suspend";
      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
      power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
      #address-cells = <1>;
      #size-cells = <1>;
      dma-ranges = <0x40000000 0x40000000 0xc0000000>;
      ranges;

      usb@38100000 {
        compatible = "snps,dwc3";
        reg = <0x38100000 0x10000>;
        clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
                 <&clk IMX8MP_CLK_USB_CORE_REF>,
                 <&clk IMX8MP_CLK_USB_ROOT>;
        clock-names = "bus_early", "ref", "suspend";
        assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
        assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
        assigned-clock-rates = <500000000>;
        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
        phys = <&usb3_phy0>, <&usb3_phy0>;
        phy-names = "usb2-phy", "usb3-phy";
        snps,dis-u2-freeclk-exists-quirk;
      };
    };