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Linux 6.18.37 · Devicetree Bindings

Lantiq XWAY Pinmux Controller

AMAZON·DANUBE·xRX 계열의 mux와 pinconf binding입니다.

Source pathDocumentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt
Source versionLinux v6.18.37
TranslationDUJINLABS 전문 번역 + 해설

요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.

1. 요약·해설

원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.

요약과 해설

lantiq,pinctrl-xway.txt:1-158

Chip별 group/function 목록, pin 이름 범위와 DANUBE GPIO 예제를 보존합니다.

2. 영어 원문 전체

번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.

원문 전체 펼치기
1 Lantiq XWAY pinmux controller
2
3 Required properties:
4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
5 "ase" (XWAY AMAZON Family)
6 "danube" (XWAY DANUBE Family)
7 "xrx100" (XWAY xRX100 Family)
8 "xrx200" (XWAY xRX200 Family)
9 "xrx300" (XWAY xRX300 Family)
10 - reg: Should contain the physical address and length of the gpio/pinmux
11 register range
12
13 Please refer to pinctrl-bindings.txt in this directory for details of the
14 common pinctrl bindings used by client devices, including the meaning of the
15 phrase "pin configuration node".
16
17 Lantiq's pin configuration nodes act as a container for an arbitrary number of
18 subnodes. Each of these subnodes represents some desired configuration for a
19 pin, a group, or a list of pins or groups. This configuration can include the
20 mux function to select on those group(s), and two pin configuration parameters:
21 pull-up and open-drain
22
23 The name of each subnode is not important as long as it is unique; all subnodes
24 should be enumerated and processed purely based on their content.
25
26 Each subnode only affects those parameters that are explicitly listed. In
27 other words, a subnode that lists a mux function but no pin configuration
28 parameters implies no information about any pin configuration parameters.
29 Similarly, a pin subnode that describes a pullup parameter implies no
30 information about e.g. the mux function.
31
32 We support 2 types of nodes.
33
34 Definition of mux function groups:
35
36 Required subnode-properties:
37 - lantiq,groups : An array of strings. Each string contains the name of a group.
38 Valid values for these names are listed below.
39 - lantiq,function: A string containing the name of the function to mux to the
40 group. Valid values for function names are listed below.
41
42 Valid values for group and function names:
43
44 AMAZON:
45 mux groups:
46 exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2,
47 spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0,
48 clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2
49
50 functions:
51 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
52
53 DANUBE:
54 mux groups:
55 exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
57 spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
58 gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3,
59 req1, req2, req3, dfe led0, dfe led1
60
61 functions:
62 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
63
64 xRX100:
65 mux groups:
66 exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
67 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
68 spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
69 spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
70 clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
71 dfe led0, dfe led1
72
73 functions:
74 spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
75
76 xRX200:
77 mux groups:
78 exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
79 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
80 spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
81 spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts,
82 usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di,
83 usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2,
84 stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1,
85 gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1,
86 gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2
87
88 functions:
89 spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
90
91 xRX300:
92 mux groups:
93 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
94 nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
95 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
96 spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx,
97 usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2,
98 mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1
99
100 functions:
101 spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
102
103
104 Definition of pin configurations:
105
106 Required subnode-properties:
107 - lantiq,pins : An array of strings. Each string contains the name of a pin.
108 Valid values for these names are listed below.
109
110 Optional subnode-properties:
111 - lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
112 0: none, 1: down, 2: up.
113 - lantiq,open-drain: Boolean, enables open-drain on the defined pin.
114
115 Valid values for AMAZON pin names:
116 Pinconf pins can be referenced via the names io0-io31.
117
118 Valid values for DANUBE pin names:
119 Pinconf pins can be referenced via the names io0-io31.
120
121 Valid values for xRX100 pin names:
122 Pinconf pins can be referenced via the names io0-io55.
123
124 Valid values for xRX200 pin names:
125 Pinconf pins can be referenced via the names io0-io49.
126
127 Valid values for xRX300 pin names:
128 Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11,
129 io13-io19,io23-io27,io34-io36,
130 io42-io43,io48-io61.
131
132 Example:
133 gpio: pinmux@e100b10 {
134 compatible = "lantiq,danube-pinctrl";
135 pinctrl-names = "default";
136 pinctrl-0 = <&state_default>;
137
138 #gpio-cells = <2>;
139 gpio-controller;
140 reg = <0xE100B10 0xA0>;
141
142 state_default: pinmux {
143 stp {
144 lantiq,groups = "stp";
145 lantiq,function = "stp";
146 };
147 pci {
148 lantiq,groups = "gnt1";
149 lantiq,function = "pci";
150 };
151 conf_out {
152 lantiq,pins = "io4", "io5", "io6"; /* stp */
153 lantiq,open-drain;
154 lantiq,pull = <0>;
155 };
156 };
157 };
158
159

3. 한국어 전문 번역

영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.

Lantiq XWAY controller 속성

1-15

Lantiq XWAY pinmux controller의 `compatible` 형식은 `lantiq,<chip>-pinctrl`입니다. `<chip>`은 XWAY AMAZON 계열의 `ase`, DANUBE 계열의 `danube`, xRX100·xRX200·xRX300 계열의 `xrx100`, `xrx200`, `xrx300` 중 하나입니다.

`reg`에는 GPIO/pinmux register 범위의 물리 주소와 길이를 지정합니다. 공통 client pinctrl binding과 `pin configuration node` 정의는 `pinctrl-bindings.txt`를 참조합니다.

XWAY configuration container

16-32

Lantiq pin configuration node는 pin, group 또는 그 목록의 configuration을 나타내는 임의 개수 하위 노드를 담습니다. 구성에는 group의 mux function과 pull-up, open-drain parameter가 포함될 수 있습니다.

하위 노드 이름은 고유하기만 하면 되고 내용으로 처리합니다. 각 노드는 명시한 parameter만 바꾸므로 mux만 지정한 노드는 pinconf를 규정하지 않고 pull-up만 지정한 노드는 mux를 규정하지 않습니다. 지원 노드 유형은 mux function group과 pin configuration 두 가지입니다.

XWAY 계열별 mux group과 function

33-102

Mux group 노드의 필수 `lantiq,groups`는 group 이름 배열이고 `lantiq,function`은 선택할 function 이름입니다.

AMAZON, DANUBE, xRX100, xRX200, xRX300 각각의 유효한 mux group과 function 전체 목록입니다.

AMAZON:
  mux groups:
    exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2,
    spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0,
    clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2

  functions:
    spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe

DANUBE:
  mux groups:
    exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
    ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
    spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
    gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3,
    req1, req2, req3, dfe led0, dfe led1

  functions:
    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe

xRX100:
  mux groups:
    exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
    ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
    spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
    spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
    clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
    dfe led0, dfe led1

  functions:
    spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe

xRX200:
  mux groups:
    exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
    ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
    spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
    spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts,
    usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di,
    usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2,
    stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1,
    gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1,
    gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2

  functions:
    spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy

xRX300:
  mux groups:
    exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
    nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
    nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
    spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx,
    usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2,
    mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1

  functions:
    spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy

XWAY pin configuration과 pin 범위

103-131

Pin configuration의 필수 `lantiq,pins`는 pin 이름 문자열 배열입니다. 선택 `lantiq,pull`은 0이면 none, 1이면 down, 2이면 up이며 Boolean `lantiq,open-drain`은 지정한 pin의 open-drain을 켭니다.

AMAZON과 DANUBE pin은 `io0`부터 `io31`, xRX100은 `io0`부터 `io55`, xRX200은 `io0`부터 `io49` 이름으로 참조합니다.

xRX300은 `io0-io1`, `io3-io6`, `io8-io11`, `io13-io19`, `io23-io27`, `io34-io36`, `io42-io43`, `io48-io61` 범위의 pin 이름을 지원합니다.

XWAY DANUBE 예제

132-158

예제는 DANUBE controller를 GPIO controller로 선언하고 기본 상태에서 STP와 PCI grant group을 mux합니다. `io4`, `io5`, `io6`에는 open-drain을 활성화하고 pull을 사용하지 않습니다.

gpio: pinmux@e100b10 {
        compatible = "lantiq,danube-pinctrl";
        pinctrl-names = "default";
        pinctrl-0 = <&state_default>;

        #gpio-cells = <2>;
        gpio-controller;
        reg = <0xE100B10 0xA0>;

        state_default: pinmux {
                stp {
                        lantiq,groups = "stp";
                        lantiq,function = "stp";
                };
                pci {
                        lantiq,groups = "gnt1";
                        lantiq,function = "pci";
                };
                conf_out {
                        lantiq,pins = "io4", "io5", "io6"; /* stp */
                        lantiq,open-drain;
                        lantiq,pull = <0>;
                };
        };
};