TI DA8XX CFGCHIP clocks | Linux 6.18.37

요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.

1. 요약·해설

원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.

요약과 해설

da8xx-cfgchip.txt:1-93

CFGCHIP register의 다섯 clock gate 및 source 선택 기능을 설명합니다.

2. 영어 원문 전체

번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.

원문 전체 펼치기

1 Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks

3 TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of

4 registers call CFGCHIPn. Some of these registers function as clock

5 gates. This document describes the bindings for those clocks.

7 All of the clock nodes described below must be child nodes of a CFGCHIP node

8 (compatible = "ti,da830-cfgchip").

10 USB PHY clocks

11 --------------

12 Required properties:

13 - compatible: shall be "ti,da830-usb-phy-clocks".

14 - #clock-cells: from common clock binding; shall be set to 1.

15 - clocks: phandles to the parent clocks corresponding to clock-names

16 - clock-names: shall be "fck", "usb_refclkin", "auxclk"

18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz

19 clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.

21 eHRPWM Time Base Clock (TBCLK)

22 ------------------------------

23 Required properties:

24 - compatible: shall be "ti,da830-tbclksync".

25 - #clock-cells: from common clock binding; shall be set to 0.

26 - clocks: phandle to the parent clock

27 - clock-names: shall be "fck"

29 PLL DIV4.5 divider

30 ------------------

31 Required properties:

32 - compatible: shall be "ti,da830-div4p5ena".

33 - #clock-cells: from common clock binding; shall be set to 0.

34 - clocks: phandle to the parent clock

35 - clock-names: shall be "pll0_pllout"

37 EMIFA clock source (ASYNC1)

38 ---------------------------

39 Required properties:

40 - compatible: shall be "ti,da850-async1-clksrc".

41 - #clock-cells: from common clock binding; shall be set to 0.

42 - clocks: phandles to the parent clocks corresponding to clock-names

43 - clock-names: shall be "pll0_sysclk3", "div4.5"

45 ASYNC3 clock source

46 -------------------

47 Required properties:

48 - compatible: shall be "ti,da850-async3-clksrc".

49 - #clock-cells: from common clock binding; shall be set to 0.

50 - clocks: phandles to the parent clocks corresponding to clock-names

51 - clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"

53 Examples:

55 cfgchip: syscon@1417c {

56 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";

57 reg = <0x1417c 0x14>;

59 usb_phy_clk: usb-phy-clocks {

60 compatible = "ti,da830-usb-phy-clocks";

61 #clock-cells = <1>;

62 clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;

63 clock-names = "fck", "usb_refclkin", "auxclk";

64 };

65 ehrpwm_tbclk: ehrpwm_tbclk {

66 compatible = "ti,da830-tbclksync";

67 #clock-cells = <0>;

68 clocks = <&psc1 17>;

69 clock-names = "fck";

70 };

71 div4p5_clk: div4.5 {

72 compatible = "ti,da830-div4p5ena";

73 #clock-cells = <0>;

74 clocks = <&pll0_pllout>;

75 clock-names = "pll0_pllout";

76 };

77 async1_clk: async1 {

78 compatible = "ti,da850-async1-clksrc";

79 #clock-cells = <0>;

80 clocks = <&pll0_sysclk 3>, <&div4p5_clk>;

81 clock-names = "pll0_sysclk3", "div4.5";

82 };

83 async3_clk: async3 {

84 compatible = "ti,da850-async3-clksrc";

85 #clock-cells = <0>;

86 clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;

87 clock-names = "pll0_sysclk2", "pll1_sysclk2";

88 };

89 };

91 Also see:

92 - Documentation/devicetree/bindings/clock/clock-bindings.txt

3. 한국어 전문 번역

영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.

DA8XX CFGCHIP와 USB PHY clocks

1-20

TI DA8XX, OMAP-L13X, AM17XX 및 AM18XX SoC의 CFGCHIP clock 바인딩입니다. 범용 CFGCHIPn register 중 일부가 clock gate로 동작합니다. 아래 모든 clock node는 `compatible = "ti,da830-cfgchip"`인 CFGCHIP node의 child여야 합니다.

USB PHY clock child의 `compatible`은 `ti,da830-usb-phy-clocks`, `#clock-cells`는 1입니다. Parent `clocks`는 `clock-names`의 `fck`, `usb_refclkin`, `auxclk`과 순서대로 대응합니다.

이 node는 output 두 개를 제공합니다. Index 0은 USB 2.0 PHY 48 MHz clock이고 index 1은 USB 1.1 PHY 48 MHz clock입니다.

DA8XX CFGCHIP child clocks

Childcompatible#clock-cells

USB PHY 48 MHz outputsti,da830-usb-phy-clocks1

eHRPWM TBCLKti,da830-tbclksync0

PLL DIV4.5ti,da830-div4p5ena0

EMIFA ASYNC1ti,da850-async1-clksrc0

ASYNC3ti,da850-async3-clksrc0

CFGCHIP register가 제공하는 다섯 clock 기능과 provider cell 수를 정리합니다.

TBCLK, DIV4.5와 asynchronous sources

21-52

eHRPWM time-base clock(TBCLK)은 `ti,da830-tbclksync` 0-cell provider이며 `fck` parent 하나를 받습니다. PLL DIV4.5 divider는 `ti,da830-div4p5ena` 0-cell provider이고 `pll0_pllout` parent 하나를 받습니다.

EMIFA ASYNC1 source는 `ti,da850-async1-clksrc`이며 `pll0_sysclk3`와 `div4.5` 두 parent를 선택합니다. ASYNC3 source는 `ti,da850-async3-clksrc`이며 `pll0_sysclk2`와 `pll1_sysclk2` 두 parent를 선택합니다. 두 source 모두 `#clock-cells`는 0입니다.

CFGCHIP child 구성 예제

53-93

예제는 `syscon`, `simple-mfd` 기능을 함께 가진 `cfgchip` parent 아래에 USB PHY, TBCLK, DIV4.5, ASYNC1, ASYNC3의 다섯 child를 구성합니다. 각 `clocks` entry와 `clock-names` entry의 순서를 일치시켜야 합니다.

cfgchip: syscon@1417c {
        compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
        reg = <0x1417c 0x14>;

        usb_phy_clk: usb-phy-clocks {
                compatible = "ti,da830-usb-phy-clocks";
                #clock-cells = <1>;
                clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
                clock-names = "fck", "usb_refclkin", "auxclk";
        };
        ehrpwm_tbclk: ehrpwm_tbclk {
                compatible = "ti,da830-tbclksync";
                #clock-cells = <0>;
                clocks = <&psc1 17>;
                clock-names = "fck";
        };
        div4p5_clk: div4.5 {
                compatible = "ti,da830-div4p5ena";
                #clock-cells = <0>;
                clocks = <&pll0_pllout>;
                clock-names = "pll0_pllout";
        };
        async1_clk: async1 {
                compatible = "ti,da850-async1-clksrc";
                #clock-cells = <0>;
                clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
                clock-names = "pll0_sysclk3", "div4.5";
        };
        async3_clk: async3 {
                compatible = "ti,da850-async3-clksrc";
                #clock-cells = <0>;
                clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
                clock-names = "pll0_sysclk2", "pll1_sysclk2";
        };
};

공통 clock 속성은 `Documentation/devicetree/bindings/clock/clock-bindings.txt`를 함께 참조합니다.