요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
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.. SPDX-License-Identifier: GPL-2.0
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RISC-V Hardware Probing Interface
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---------------------------------
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The RISC-V hardware probing interface is based around a single syscall, which
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is defined in <asm/hwprobe.h>::
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struct riscv_hwprobe {
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__s64 key;
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__u64 value;
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};
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long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
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size_t cpusetsize, cpu_set_t *cpus,
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unsigned int flags);
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The arguments are split into three groups: an array of key-value pairs, a CPU
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set, and some flags. The key-value pairs are supplied with a count. Userspace
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must prepopulate the key field for each element, and the kernel will fill in the
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value if the key is recognized. If a key is unknown to the kernel, its key field
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will be cleared to -1, and its value set to 0. The CPU set is defined by
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CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
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arch, impl), the returned value will only be valid if all CPUs in the given set
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have the same value. Otherwise -1 will be returned. For boolean-like keys, the
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value returned will be a logical AND of the values for the specified CPUs.
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Usermode can supply NULL for ``cpus`` and 0 for ``cpusetsize`` as a shortcut for
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all online CPUs. The currently supported flags are:
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* :c:macro:`RISCV_HWPROBE_WHICH_CPUS`: This flag basically reverses the behavior
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of sys_riscv_hwprobe(). Instead of populating the values of keys for a given
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set of CPUs, the values of each key are given and the set of CPUs is reduced
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by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
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How matching is done depends on the key type. For value-like keys, matching
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means to be the exact same as the value. For boolean-like keys, matching
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means the result of a logical AND of the pair's value with the CPU's value is
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exactly the same as the pair's value. Additionally, when ``cpus`` is an empty
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set, then it is initialized to all online CPUs which fit within it, i.e. the
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CPU set returned is the reduction of all the online CPUs which can be
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represented with a CPU set of size ``cpusetsize``.
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All other flags are reserved for future compatibility and must be zero.
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On success 0 is returned, on failure a negative error code is returned.
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The following keys are defined:
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* :c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Contains the value of ``mvendorid``,
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as defined by the RISC-V privileged architecture specification.
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* :c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contains the value of ``marchid``, as
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defined by the RISC-V privileged architecture specification.
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* :c:macro:`RISCV_HWPROBE_KEY_MIMPID`: Contains the value of ``mimpid``, as
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defined by the RISC-V privileged architecture specification.
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* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base
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user-visible behavior that this kernel supports. The following base user ABIs
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are defined:
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* :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or
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rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the
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privileged ISA, with the following known exceptions (more exceptions may be
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added, but only if it can be demonstrated that the user ABI is not broken):
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* The ``fence.i`` instruction cannot be directly executed by userspace
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programs (it may still be executed in userspace via a
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kernel-controlled mechanism such as the vDSO).
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* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
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that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
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base system behavior.
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* :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as
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defined by commit cd20cee ("FMIN/FMAX now implement
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minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
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by version 2.2 of the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by
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version 1.0 of the RISC-V Vector extension manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
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supported, as defined in version 1.0 of the Bit-Manipulation ISA
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extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
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in version 1.0 of the Bit-Manipulation ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
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in version 1.0 of the Bit-Manipulation ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
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ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
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in version 1.0 of the Bit-Manipulation ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
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in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported
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as defined in the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
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supported as defined in the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
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is supported as defined in the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as
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defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
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("Remove draft warnings from Zvfh[min]").
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* :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as
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defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
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("Remove draft warnings from Zvfh[min]").
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* :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as
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defined in the RISC-V ISA manual starting from commit 056b6ff467c7
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("Zfa is ratified").
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* :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as
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defined in the RISC-V ISA manual starting from commit 5618fb5a216b
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("Ztso is now ratified.")
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* :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as
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defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
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from commit 5059e0ca641c ("update to ratified").
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* :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0
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is supported as defined in the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
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defined in the RISC-V Integer Conditional (Zicond) operations extension
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manual starting from commit 95cf1f9 ("Add changes requested by Ved
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during signoff")
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* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is
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supported as defined in the RISC-V ISA manual starting from commit
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d8ab5c78c207 ("Zihintpause is ratified").
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* :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0
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is supported as defined in the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
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supported, as defined by version 1.0 of the RISC-V Vector extension manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
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supported, as defined by version 1.0 of the RISC-V Vector extension manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
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supported, as defined by version 1.0 of the RISC-V Vector extension manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
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supported, as defined by version 1.0 of the RISC-V Vector extension manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
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supported, as defined by version 1.0 of the RISC-V Vector extension manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
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supported as defined in the RISC-V ISA manual starting from commit
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58220614a5f ("Zimop is ratified/1.0").
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* :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard
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extensions for code size reduction, as ratified in commit 8be3419c1c0
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("Zcf doesn't exist on RV64 as it contains no instructions") of
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riscv-code-size-reduction.
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* :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard
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extensions for code size reduction, as ratified in commit 8be3419c1c0
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("Zcf doesn't exist on RV64 as it contains no instructions") of
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riscv-code-size-reduction.
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* :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard
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extensions for code size reduction, as ratified in commit 8be3419c1c0
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("Zcf doesn't exist on RV64 as it contains no instructions") of
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riscv-code-size-reduction.
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* :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard
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extensions for code size reduction, as ratified in commit 8be3419c1c0
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("Zcf doesn't exist on RV64 as it contains no instructions") of
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riscv-code-size-reduction.
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* :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is
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supported as defined in the RISC-V ISA manual starting from commit
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c732a4f39a4 ("Zcmop is ratified/1.0").
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* :c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as
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ratified in commit 98918c844281 ("Merge pull request #1217 from
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riscv/zawrs") of riscv-isa-manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as
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defined in the in the RISC-V ISA manual starting from commit e87412e621f1
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("integrate Zaamo and Zalrsc text (#1304)").
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* :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
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defined in the in the RISC-V ISA manual starting from commit e87412e621f1
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("integrate Zaamo and Zalrsc text (#1304)").
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* :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
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defined in version 1.0 of the RISC-V Pointer Masking extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
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defined in the RISC-V ISA manual starting from commit 4dc23d6229de
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("Added Chapter title to BF16").
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* :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
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defined in the RISC-V ISA manual starting from commit 4dc23d6229de
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("Added Chapter title to BF16").
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* :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
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defined in the RISC-V ISA manual starting from commit 4dc23d6229de
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("Added Chapter title to BF16").
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* :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
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ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
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* :c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as
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ratified in commit 49f49c842ff9 ("Update to Rafified state") of
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riscv-zabha.
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* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
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:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
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mistakenly classified as a bitmask rather than a value.
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* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing
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the performance of misaligned scalar native word accesses on the selected set
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of processors.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of
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misaligned scalar accesses is unknown.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar
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accesses are emulated via software, either in or below the kernel. These
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accesses are always extremely slow.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native
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word sized accesses are slower than the equivalent quantity of byte
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accesses. Misaligned accesses may be supported directly in hardware, or
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trapped and emulated by software.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native
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word sized accesses are faster than the equivalent quantity of byte
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accesses.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar
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accesses are not supported at all and will generate a misaligned address
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fault.
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* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
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represents the size of the Zicboz block in bytes.
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* :c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which
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represent the highest userspace virtual address usable.
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* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.
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* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the
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performance of misaligned vector accesses on the selected set of processors.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned
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vector accesses is unknown.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector
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registers are slower than the equivalent quantity of byte accesses via vector registers.
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Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector
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registers are faster than the equivalent quantity of byte accesses via vector registers.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are
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not supported at all and will generate a misaligned address fault.
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* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the
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mips vendor extensions that are compatible with the
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:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
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* MIPS
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor
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extension is supported in the MIPS ISA extensions spec.
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* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the
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thead vendor extensions that are compatible with the
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:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
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* T-HEAD
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor
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extension is supported in the T-Head ISA extensions spec starting from
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commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
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* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
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represents the size of the Zicbom block in bytes.
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* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`: A bitmask containing the
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sifive vendor extensions that are compatible with the
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:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
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* SIFIVE
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor
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extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
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Extensions Specification.
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
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extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
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Instruction Extensions Specification.
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
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vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
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Clip Instructions Extensions Specification.
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
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vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
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Instruction Extensions Specification.
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
Hardware probing syscall
1-17RISC-V hardware probing interface는 `<asm/hwprobe.h>`에 정의된 단일 syscall을 중심으로 구성됩니다. `riscv_hwprobe` pair는 signed 64-bit `key`와 unsigned 64-bit `value`를 담습니다.
struct riscv_hwprobe {
__s64 key;
__u64 value;
};
long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
size_t cpusetsize, cpu_set_t *cpus,
unsigned int flags);Pair와 CPU set semantics
18-29Argument는 key-value pair array, CPU set, flags 세 그룹입니다. Userspace는 `pair_count`만큼의 element에서 `key`를 미리 채우고 kernel은 인식한 key의 `value`를 채웁니다. Kernel이 모르는 key는 `key=-1`, `value=0`으로 바뀝니다.
CPU set은 `CPU_SET(3)` 형식이며 `cpusetsize` byte입니다. Vendor·architecture·implementation 같은 value-like key는 지정된 모든 CPU가 같은 값을 가질 때만 유효하고 그렇지 않으면 `-1`을 반환합니다. Boolean-like key는 지정 CPU 값의 logical AND를 반환합니다.
Userspace가 `cpus=NULL`, `cpusetsize=0`을 전달하면 모든 online CPU를 뜻하는 shortcut입니다.
Userspace key array→CPU set→`sys_riscv_hwprobe()`
Value-like key→모든 CPU 값 비교→같으면 value, 다르면 -1
Boolean-like key→CPU별 bitmask→Logical AND
미리 채운 key와 CPU set을 kernel이 공통 value로 변환합니다.
RISCV_HWPROBE_WHICH_CPUS
30-45`RISCV_HWPROBE_WHICH_CPUS`는 `sys_riscv_hwprobe()`의 동작을 뒤집습니다. CPU set에서 key value를 조회하는 대신 userspace가 key-value pair를 주고, syscall은 모든 pair와 일치하는 CPU만 남기도록 set을 축소합니다.
Value-like key는 정확히 같은 값이어야 합니다. Boolean-like key는 pair value와 CPU value를 AND한 결과가 pair value와 정확히 같아야 하므로 요청한 bit가 모두 존재해야 합니다.
`cpus`가 empty set이면 `cpusetsize`로 표현할 수 있는 모든 online CPU로 초기화한 뒤 조건에 맞는 CPU만 반환합니다. 그 밖의 flag는 future compatibility를 위해 reserved이며 반드시 0이어야 합니다.
성공하면 0, 실패하면 negative error code를 반환합니다.
Requested key-value pairs→Input CPU set 또는 empty set
Exact value match→Requested boolean bits 포함
Reduced matching CPU set
원하는 capability를 만족하는 CPU set을 얻는 역방향 query입니다.
Identity와 base behavior key
46-69| Macro | 반환 의미 |
|---|---|
| `RISCV_HWPROBE_KEY_MVENDORID` | RISC-V privileged architecture specification의 `mvendorid` 값 |
| `RISCV_HWPROBE_KEY_MARCHID` | RISC-V privileged architecture specification의 `marchid` 값 |
| `RISCV_HWPROBE_KEY_MIMPID` | RISC-V privileged architecture specification의 `mimpid` 값 |
| `RISCV_HWPROBE_KEY_BASE_BEHAVIOR` | Kernel이 지원하는 기본 userspace-visible behavior bitmask |
| `RISCV_HWPROBE_BASE_BEHAVIOR_IMA` | User ISA 2.2와 privileged ISA 1.10의 rv32ima/rv64ima ABI |
| `RISCV_HWPROBE_KEY_IMA_EXT_0` | `RISCV_HWPROBE_BASE_BEHAVIOR_IMA`와 호환되는 extension bitmask |
`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`는 user ISA version 2.2와 privileged ISA version 1.10의 rv32ima 또는 rv64ima를 지원합니다. User ABI를 깨지 않는다고 입증되는 예외는 추가될 수 있습니다.
현재 알려진 예외로 userspace program은 `fence.i` instruction을 직접 실행할 수 없습니다. 다만 vDSO 같은 kernel-controlled mechanism을 통해 userspace에서 실행할 수는 있습니다.
IMA·bit-manipulation·scalar crypto extensions
70-125`RISCV_HWPROBE_KEY_IMA_EXT_0` bitmask의 다음 bit들은 IMA base behavior와 호환되는 floating-point, compressed, vector, bit-manipulation, scalar-cryptography extension 지원을 나타냅니다.
| Macro | Extension | 기준 specification |
|---|---|---|
| `RISCV_HWPROBE_IMA_FD` | F/D | RISC-V ISA manual commit `cd20cee` (`FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNum`) |
| `RISCV_HWPROBE_IMA_C` | C | RISC-V ISA manual version 2.2 |
| `RISCV_HWPROBE_IMA_V` | V | RISC-V Vector extension manual version 1.0 |
| `RISCV_HWPROBE_EXT_ZBA` | Zba | Bit-Manipulation ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZBB` | Zbb | Bit-Manipulation ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZBS` | Zbs | Bit-Manipulation ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZICBOZ` | Zicboz | riscv-CMOs commit `3dd606f` (`Create cmobase-v1.0.pdf`) |
| `RISCV_HWPROBE_EXT_ZBC` | Zbc | Bit-Manipulation ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZBKB` | Zbkb | Scalar Crypto ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZBKC` | Zbkc | Scalar Crypto ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZBKX` | Zbkx | Scalar Crypto ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZKND` | Zknd | Scalar Crypto ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZKNE` | Zkne | Scalar Crypto ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZKNH` | Zknh | Scalar Crypto ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZKSED` | Zksed | Scalar Crypto ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZKSH` | Zksh | Scalar Crypto ISA extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZKT` | Zkt | Scalar Crypto ISA extensions version 1.0 |
Vector crypto와 floating-point extensions
126-180다음 bit들은 vector cryptography, half-precision floating point, non-temporal locality hint, additional floating-point, total-store-order extension 지원을 나타냅니다.
| Macro | Extension | 기준 specification |
|---|---|---|
| `RISCV_HWPROBE_EXT_ZVBB` | Zvbb | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZVBC` | Zvbc | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZVKB` | Zvkb | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZVKG` | Zvkg | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZVKNED` | Zvkned | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZVKNHA` | Zvknha | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZVKNHB` | Zvknhb | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZVKSED` | Zvksed | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZVKSH` | Zvksh | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZVKT` | Zvkt | RISC-V Cryptography Extensions Volume II version 1.0 |
| `RISCV_HWPROBE_EXT_ZFH` | Zfh | RISC-V ISA manual version 1.0 |
| `RISCV_HWPROBE_EXT_ZFHMIN` | Zfhmin | RISC-V ISA manual version 1.0 |
| `RISCV_HWPROBE_EXT_ZIHINTNTL` | Zihintntl | RISC-V ISA manual version 1.0 |
| `RISCV_HWPROBE_EXT_ZVFH` | Zvfh | RISC-V Vector manual commit `e2ccd0548d6c` (`Remove draft warnings from Zvfh[min]`) |
| `RISCV_HWPROBE_EXT_ZVFHMIN` | Zvfhmin | RISC-V Vector manual commit `e2ccd0548d6c` (`Remove draft warnings from Zvfh[min]`) |
| `RISCV_HWPROBE_EXT_ZFA` | Zfa | RISC-V ISA manual commit `056b6ff467c7` (`Zfa is ratified`) |
| `RISCV_HWPROBE_EXT_ZTSO` | Ztso | RISC-V ISA manual commit `5618fb5a216b` (`Ztso is now ratified.`) |
Atomic·counter·vector subset·code-size extensions
181-238다음 bit들은 compare-and-swap, counter, conditional operation, pause hint, performance monitor, embedded vector subset, may-be-operation, Zc* code-size-reduction extension 지원을 나타냅니다.
| Macro | Extension | 기준 specification |
|---|---|---|
| `RISCV_HWPROBE_EXT_ZACAS` | Zacas | Atomic Compare-and-Swap manual commit `5059e0ca641c` (`update to ratified`) |
| `RISCV_HWPROBE_EXT_ZICNTR` | Zicntr | RISC-V ISA manual version 2.0 |
| `RISCV_HWPROBE_EXT_ZICOND` | Zicond | Integer Conditional operations manual commit `95cf1f9` (`Add changes requested by Ved during signoff`) |
| `RISCV_HWPROBE_EXT_ZIHINTPAUSE` | Zihintpause | RISC-V ISA manual commit `d8ab5c78c207` (`Zihintpause is ratified`) |
| `RISCV_HWPROBE_EXT_ZIHPM` | Zihpm | RISC-V ISA manual version 2.0 |
| `RISCV_HWPROBE_EXT_ZVE32X` | Zve32x | RISC-V Vector extension manual version 1.0 |
| `RISCV_HWPROBE_EXT_ZVE32F` | Zve32f | RISC-V Vector extension manual version 1.0 |
| `RISCV_HWPROBE_EXT_ZVE64X` | Zve64x | RISC-V Vector extension manual version 1.0 |
| `RISCV_HWPROBE_EXT_ZVE64F` | Zve64f | RISC-V Vector extension manual version 1.0 |
| `RISCV_HWPROBE_EXT_ZVE64D` | Zve64d | RISC-V Vector extension manual version 1.0 |
| `RISCV_HWPROBE_EXT_ZIMOP` | Zimop | RISC-V ISA manual commit `58220614a5f` (`Zimop is ratified/1.0`) |
| `RISCV_HWPROBE_EXT_ZCA` | Zca | riscv-code-size-reduction commit `8be3419c1c0` (`Zcf doesn't exist on RV64 as it contains no instructions`) |
| `RISCV_HWPROBE_EXT_ZCB` | Zcb | riscv-code-size-reduction commit `8be3419c1c0` (`Zcf doesn't exist on RV64 as it contains no instructions`) |
| `RISCV_HWPROBE_EXT_ZCD` | Zcd | riscv-code-size-reduction commit `8be3419c1c0` (`Zcf doesn't exist on RV64 as it contains no instructions`) |
| `RISCV_HWPROBE_EXT_ZCF` | Zcf | riscv-code-size-reduction commit `8be3419c1c0` (`Zcf doesn't exist on RV64 as it contains no instructions`) |
추가 ratified extensions
239-277다음 bit들은 Zcmop, wait-on-reservation-set, split atomic, pointer masking, bfloat16, cache-block management, byte/halfword atomic extension 지원을 나타냅니다.
| Macro | Extension | 기준 specification |
|---|---|---|
| `RISCV_HWPROBE_EXT_ZCMOP` | Zcmop | RISC-V ISA manual commit `c732a4f39a4` (`Zcmop is ratified/1.0`) |
| `RISCV_HWPROBE_EXT_ZAWRS` | Zawrs | riscv-isa-manual commit `98918c844281` (`Merge pull request #1217 from riscv/zawrs`) |
| `RISCV_HWPROBE_EXT_ZAAMO` | Zaamo | RISC-V ISA manual commit `e87412e621f1` (`integrate Zaamo and Zalrsc text (#1304)`) |
| `RISCV_HWPROBE_EXT_ZALRSC` | Zalrsc | RISC-V ISA manual commit `e87412e621f1` (`integrate Zaamo and Zalrsc text (#1304)`) |
| `RISCV_HWPROBE_EXT_SUPM` | Supm | RISC-V Pointer Masking extensions version 1.0 |
| `RISCV_HWPROBE_EXT_ZFBFMIN` | Zfbfmin | RISC-V ISA manual commit `4dc23d6229de` (`Added Chapter title to BF16`) |
| `RISCV_HWPROBE_EXT_ZVFBFMIN` | Zvfbfmin | RISC-V ISA manual commit `4dc23d6229de` (`Added Chapter title to BF16`) |
| `RISCV_HWPROBE_EXT_ZVFBFWMA` | Zvfbfwma | RISC-V ISA manual commit `4dc23d6229de` (`Added Chapter title to BF16`) |
| `RISCV_HWPROBE_EXT_ZICBOM` | Zicbom | riscv-CMOs commit `3dd606f` (`Create cmobase-v1.0.pdf`) |
| `RISCV_HWPROBE_EXT_ZABHA` | Zabha | riscv-zabha commit `49f49c842ff9` (`Update to Rafified state`) |
Misaligned scalar performance
278-304`RISCV_HWPROBE_KEY_CPUPERF_0`은 deprecated입니다. `RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`와 비슷한 값을 반환하지만 value가 아니라 bitmask로 잘못 분류되었습니다.
`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`는 선택한 processor set에서 native word 크기 misaligned scalar access의 성능을 설명하는 enum입니다.
| Enum | 의미 |
|---|---|
| `RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN` | Misaligned scalar access 성능을 알 수 없음 |
| `RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED` | Kernel 내부 또는 하위 layer의 software emulation이며 항상 매우 느림 |
| `RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW` | Native word access가 같은 양의 byte access보다 느림. Hardware 처리 또는 trap/emulation일 수 있음 |
| `RISCV_HWPROBE_MISALIGNED_SCALAR_FAST` | Native word access가 같은 양의 byte access보다 빠름 |
| `RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED` | 지원하지 않으며 misaligned address fault 발생 |
Block size, address, time과 vector performance
305-329| Key | 반환 의미 |
|---|---|
| `RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE` | Byte 단위 Zicboz block size를 나타내는 unsigned int |
| `RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS` | Userspace가 사용할 수 있는 가장 높은 virtual address를 나타내는 unsigned long |
| `RISCV_HWPROBE_KEY_TIME_CSR_FREQ` | `time CSR` frequency, 단위 Hz |
| `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF` | 선택한 processor set의 misaligned vector access 성능 enum |
`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`는 선택한 processor set의 misaligned vector access 성능을 다음 enum으로 분류합니다. Slow와 fast 비교는 vector register를 통한 32-bit misaligned access와 같은 양의 vector byte access를 기준으로 합니다. Slow는 hardware 지원 또는 trap/software emulation일 수 있습니다.
| Enum | 의미 |
|---|---|
| `RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN` | Misaligned vector access 성능을 알 수 없음 |
| `RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW` | Vector register의 32-bit misaligned access가 같은 양의 vector byte access보다 느림 |
| `RISCV_HWPROBE_MISALIGNED_VECTOR_FAST` | Vector register의 32-bit misaligned access가 같은 양의 vector byte access보다 빠름 |
| `RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED` | 지원하지 않으며 misaligned address fault 발생 |
UNKNOWN→성능 미확인
EMULATED 또는 SLOW→Software emulation 또는 byte access보다 느림
FAST→Byte access보다 빠름
UNSUPPORTED→Misaligned address fault
Scalar와 vector key가 공통적으로 제공하는 성능 분류입니다.
Vendor extensions와 Zicbom block size
330-372`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`, `RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`, `RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`은 각각 IMA base behavior와 호환되는 vendor extension bitmask입니다.
| Macro | Vendor | 지원 의미 |
|---|---|---|
| `RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0` | MIPS | `RISCV_HWPROBE_BASE_BEHAVIOR_IMA`와 호환되는 MIPS vendor-extension bitmask |
| `RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL` | MIPS | MIPS ISA extensions specification의 xmipsexectl |
| `RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0` | T-HEAD | `RISCV_HWPROBE_BASE_BEHAVIOR_IMA`와 호환되는 T-HEAD vendor-extension bitmask |
| `RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR` | T-HEAD | T-Head ISA extensions commit `a18c801634` (`Add T-Head VECTOR vendor extension. `)부터의 xtheadvector |
| `RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0` | SiFive | `RISCV_HWPROBE_BASE_BEHAVIOR_IMA`와 호환되는 SiFive vendor-extension bitmask |
| `RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD` | SiFive | SiFive Int8 Matrix Multiplication Extensions Specification version 1.1의 Xsfqmaccdod |
| `RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ` | SiFive | SiFive Int8 Matrix Multiplication Instruction Extensions Specification version 1.1의 Xsfqmaccqoq |
| `RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF` | SiFive | SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification version 1.0의 Xsfvfnrclipxfqf |
| `RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ` | SiFive | Matrix Multiply Accumulate Instruction Extensions Specification version 1.0의 Xsfvfwmaccqqq |
`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`는 byte 단위 Zicbom block size를 반환하는 unsigned int입니다.
요약과 해설
hwprobe.rst:1-372`sys_riscv_hwprobe()`는 key-value pair와 CPU set을 함께 받아 identity value, base behavior, ISA·vendor extension bitmask, misaligned access 성능을 반환합니다. `RISCV_HWPROBE_WHICH_CPUS`는 같은 ABI를 역으로 사용해 요청 capability를 모두 만족하는 CPU set을 구합니다.