요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
1
.. _elf_hwcaps_powerpc:
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==================
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POWERPC ELF HWCAPs
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==================
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This document describes the usage and semantics of the powerpc ELF HWCAPs.
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1. Introduction
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---------------
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Some hardware or software features are only available on some CPU
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implementations, and/or with certain kernel configurations, but have no other
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discovery mechanism available to userspace code. The kernel exposes the
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presence of these features to userspace through a set of flags called HWCAPs,
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exposed in the auxiliary vector.
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Userspace software can test for features by acquiring the AT_HWCAP or
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AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
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flags are set, e.g.::
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bool floating_point_is_present(void)
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{
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unsigned long HWCAPs = getauxval(AT_HWCAP);
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if (HWCAPs & PPC_FEATURE_HAS_FPU)
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return true;
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return false;
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}
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Where software relies on a feature described by a HWCAP, it should check the
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relevant HWCAP flag to verify that the feature is present before attempting to
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make use of the feature.
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HWCAP is the preferred method to test for the presence of a feature rather
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than probing through other means, which may not be reliable or may cause
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unpredictable behaviour.
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Software that targets a particular platform does not necessarily have to
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test for required or implied features. For example if the program requires
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FPU, VMX, VSX, it is not necessary to test those HWCAPs, and it may be
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impossible to do so if the compiler generates code requiring those features.
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2. Facilities
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-------------
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The Power ISA uses the term "facility" to describe a class of instructions,
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registers, interrupts, etc. The presence or absence of a facility indicates
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whether this class is available to be used, but the specifics depend on the
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ISA version. For example, if the VSX facility is available, the VSX
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instructions that can be used differ between the v3.0B and v3.1B ISA
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versions.
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3. Categories
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-------------
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The Power ISA before v3.0 uses the term "category" to describe certain
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classes of instructions and operating modes which may be optional or
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mutually exclusive, the exact meaning of the HWCAP flag may depend on
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context, e.g., the presence of the BOOKE feature implies that the server
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category is not implemented.
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4. HWCAP allocation
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-------------------
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HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
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Specification (which will be reflected in the kernel's uapi headers).
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5. The HWCAPs exposed in AT_HWCAP
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---------------------------------
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PPC_FEATURE_32
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32-bit CPU
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PPC_FEATURE_64
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64-bit CPU (userspace may be running in 32-bit mode).
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PPC_FEATURE_601_INSTR
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The processor is PowerPC 601.
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Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")
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PPC_FEATURE_HAS_ALTIVEC
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Vector (aka Altivec, VMX) facility is available.
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PPC_FEATURE_HAS_FPU
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Floating point facility is available.
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PPC_FEATURE_HAS_MMU
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Memory management unit is present and enabled.
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PPC_FEATURE_HAS_4xxMAC
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The processor is 40x or 44x family.
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Unused in the kernel since 732b32daef80 ("powerpc: Remove core support for 40x")
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PPC_FEATURE_UNIFIED_CACHE
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The processor has a unified L1 cache for instructions and data, as
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found in NXP e200.
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Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
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PPC_FEATURE_HAS_SPE
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Signal Processing Engine facility is available.
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PPC_FEATURE_HAS_EFP_SINGLE
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Embedded Floating Point single precision operations are available.
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PPC_FEATURE_HAS_EFP_DOUBLE
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Embedded Floating Point double precision operations are available.
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PPC_FEATURE_NO_TB
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The timebase facility (mftb instruction) is not available.
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This is a 601 specific HWCAP, so if it is known that the processor
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running is not a 601, via other HWCAPs or other means, it is not
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required to test this bit before using the timebase.
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Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")
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PPC_FEATURE_POWER4
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The processor is POWER4 or PPC970/FX/MP.
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POWER4 support dropped from the kernel since 471d7ff8b51b ("powerpc/64s: Remove POWER4 support")
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PPC_FEATURE_POWER5
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The processor is POWER5.
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PPC_FEATURE_POWER5_PLUS
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The processor is POWER5+.
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PPC_FEATURE_CELL
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The processor is Cell.
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PPC_FEATURE_BOOKE
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The processor implements the embedded category ("BookE") architecture.
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PPC_FEATURE_SMT
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The processor implements SMT.
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PPC_FEATURE_ICACHE_SNOOP
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The processor icache is coherent with the dcache, and instruction storage
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can be made consistent with data storage for the purpose of executing
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instructions with the sequence (as described in, e.g., POWER9 Processor
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User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi))::
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sync
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icbi (to any address)
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isync
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PPC_FEATURE_ARCH_2_05
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The processor supports the v2.05 userlevel architecture. Processors
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supporting later architectures DO NOT set this feature.
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PPC_FEATURE_PA6T
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The processor is PA6T.
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PPC_FEATURE_HAS_DFP
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DFP facility is available.
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PPC_FEATURE_POWER6_EXT
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The processor is POWER6.
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PPC_FEATURE_ARCH_2_06
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The processor supports the v2.06 userlevel architecture. Processors
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supporting later architectures also set this feature.
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PPC_FEATURE_HAS_VSX
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VSX facility is available.
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PPC_FEATURE_PSERIES_PERFMON_COMPAT
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The processor supports architected PMU events in the range 0xE0-0xFF.
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PPC_FEATURE_TRUE_LE
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The processor supports true little-endian mode.
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PPC_FEATURE_PPC_LE
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The processor supports "PowerPC Little-Endian", that uses address
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munging to make storage access appear to be little-endian, but the
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data is stored in a different format that is unsuitable to be
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accessed by other agents not running in this mode.
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6. The HWCAPs exposed in AT_HWCAP2
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----------------------------------
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PPC_FEATURE2_ARCH_2_07
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The processor supports the v2.07 userlevel architecture. Processors
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supporting later architectures also set this feature.
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PPC_FEATURE2_HTM
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Transactional Memory feature is available.
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PPC_FEATURE2_DSCR
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DSCR facility is available.
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PPC_FEATURE2_EBB
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EBB facility is available.
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PPC_FEATURE2_ISEL
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isel instruction is available. This is superseded by ARCH_2_07 and
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later.
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PPC_FEATURE2_TAR
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TAR facility is available.
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PPC_FEATURE2_VEC_CRYPTO
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v2.07 crypto instructions are available.
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PPC_FEATURE2_HTM_NOSC
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System calls fail if called in a transactional state, see
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Documentation/arch/powerpc/syscall64-abi.rst
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PPC_FEATURE2_ARCH_3_00
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The processor supports the v3.0B / v3.0C userlevel architecture. Processors
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supporting later architectures also set this feature.
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PPC_FEATURE2_HAS_IEEE128
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IEEE 128-bit binary floating point is supported with VSX
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quad-precision instructions and data types.
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PPC_FEATURE2_DARN
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darn instruction is available.
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PPC_FEATURE2_SCV
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The scv 0 instruction may be used for system calls, see
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Documentation/arch/powerpc/syscall64-abi.rst.
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PPC_FEATURE2_HTM_NO_SUSPEND
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A limited Transactional Memory facility that does not support suspend is
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available, see Documentation/arch/powerpc/transactional_memory.rst.
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PPC_FEATURE2_ARCH_3_1
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The processor supports the v3.1 userlevel architecture. Processors
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supporting later architectures also set this feature.
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PPC_FEATURE2_MMA
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MMA facility is available.
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
POWERPC ELF HWCAPs 의미
1-9이 문서는 PowerPC ELF hardware-capability flag (`HWCAP`)의 사용법과 의미를 설명합니다.
Auxiliary vector에서 feature 확인
10-44일부 hardware/software feature는 특정 CPU implementation 또는 kernel configuration에서만 사용할 수 있지만 userspace가 알아낼 다른 mechanism이 없습니다. Kernel은 auxiliary vector에 노출되는 HWCAP flag 집합으로 feature 존재 여부를 알립니다.
Userspace는 auxiliary vector의 `AT_HWCAP` 또는 `AT_HWCAP2` entry를 얻고 관련 flag bit를 검사합니다.
bool floating_point_is_present(void)
{
unsigned long HWCAPs = getauxval(AT_HWCAP);
if (HWCAPs & PPC_FEATURE_HAS_FPU)
return true;
return false;
}Software가 HWCAP이 설명하는 feature에 의존한다면 사용 전에 해당 HWCAP flag를 검사해 실제 존재를 확인해야 합니다. 다른 probe 방식은 신뢰할 수 없거나 예측 불가능한 behavior를 일으킬 수 있으므로 HWCAP이 선호됩니다.
특정 platform을 target으로 하는 software는 필수 또는 암시된 feature를 항상 검사할 필요는 없습니다. 예를 들어 program이 FPU, VMX, VSX를 필수로 요구하고 compiler가 이미 그 instruction을 생성한다면 해당 HWCAP을 검사할 필요가 없거나 검사 자체가 불가능할 수 있습니다.
`getauxval(AT_HWCAP/AT_HWCAP2)`→Relevant flag set?→Feature 사용
Flag clear→Fallback 또는 지원 불가 처리
Auxiliary vector bit를 확인한 뒤에만 optional facility를 사용합니다.
Power ISA facility
45-54Power ISA에서 `facility`는 instruction, register, interrupt 등의 class를 뜻합니다. Facility가 존재하면 그 class를 사용할 수 있지만 세부 기능은 ISA version에 따라 달라집니다. 예를 들어 VSX facility가 있어도 v3.0B와 v3.1B에서 사용할 수 있는 VSX instruction은 서로 다릅니다.
Power ISA category
55-63Power ISA v3.0 이전에는 optional 또는 mutually-exclusive instruction class와 operating mode를 `category`라고 불렀습니다. HWCAP flag의 정확한 의미는 context에 따라 달라질 수 있습니다. 예를 들어 `BOOKE` feature가 있으면 server category가 구현되지 않았음을 뜻합니다.
HWCAP allocation
64-69HWCAP은 Power Architecture 64-Bit ELF V2 ABI Specification에 따라 할당되며 kernel UAPI header에도 반영됩니다.
`AT_HWCAP` flag
70-177| Flag | 의미 |
|---|---|
| `PPC_FEATURE_32` | 32-bit CPU |
| `PPC_FEATURE_64` | 64-bit CPU. Userspace는 32-bit mode로 실행 중일 수 있음 |
| `PPC_FEATURE_601_INSTR` | Processor가 PowerPC 601. Commit `f0ed73f3fa2c` 이후 kernel에서 사용하지 않음 |
| `PPC_FEATURE_HAS_ALTIVEC` | Vector, 즉 Altivec/VMX facility 사용 가능 |
| `PPC_FEATURE_HAS_FPU` | Floating-point facility 사용 가능 |
| `PPC_FEATURE_HAS_MMU` | MMU가 존재하고 enable됨 |
| `PPC_FEATURE_HAS_4xxMAC` | 40x 또는 44x family. Commit `732b32daef80` 이후 kernel에서 사용하지 않음 |
| `PPC_FEATURE_UNIFIED_CACHE` | NXP e200처럼 instruction/data가 unified L1 cache를 사용. Commit `39c8bf2b3cc1` 이후 kernel에서 사용하지 않음 |
| `PPC_FEATURE_HAS_SPE` | Signal Processing Engine facility 사용 가능 |
| `PPC_FEATURE_HAS_EFP_SINGLE` | Embedded Floating Point single-precision operation 사용 가능 |
| `PPC_FEATURE_HAS_EFP_DOUBLE` | Embedded Floating Point double-precision operation 사용 가능 |
| `PPC_FEATURE_NO_TB` | Timebase facility와 `mftb` instruction을 사용할 수 없음. 601 전용 HWCAP이므로 다른 방법으로 non-601임을 알면 timebase 사용 전에 검사할 필요가 없음. Commit `f0ed73f3fa2c` 이후 미사용 |
| `PPC_FEATURE_POWER4` | POWER4 또는 PPC970/FX/MP. Commit `471d7ff8b51b` 이후 POWER4 kernel support 제거 |
| `PPC_FEATURE_POWER5` | Processor가 POWER5 |
| `PPC_FEATURE_POWER5_PLUS` | Processor가 POWER5+ |
| `PPC_FEATURE_CELL` | Processor가 Cell |
| `PPC_FEATURE_BOOKE` | Processor가 embedded category인 BookE architecture를 구현 |
| `PPC_FEATURE_SMT` | Processor가 SMT를 구현 |
| `PPC_FEATURE_ICACHE_SNOOP` | I-cache와 D-cache가 coherent하며 정해진 `sync`/`icbi`/`isync` sequence로 instruction storage를 data storage와 일치시킬 수 있음 |
| `PPC_FEATURE_ARCH_2_05` | v2.05 user-level architecture 지원. 이후 architecture 지원 processor는 이 feature를 set하지 않음 |
| `PPC_FEATURE_PA6T` | Processor가 PA6T |
| `PPC_FEATURE_HAS_DFP` | DFP facility 사용 가능 |
| `PPC_FEATURE_POWER6_EXT` | Processor가 POWER6 |
| `PPC_FEATURE_ARCH_2_06` | v2.06 user-level architecture 지원. 이후 architecture도 이 feature를 set |
| `PPC_FEATURE_HAS_VSX` | VSX facility 사용 가능 |
| `PPC_FEATURE_PSERIES_PERFMON_COMPAT` | `0xE0-0xFF` 범위의 architected PMU event 지원 |
| `PPC_FEATURE_TRUE_LE` | True little-endian mode 지원 |
| `PPC_FEATURE_PPC_LE` | Address munging으로 storage access를 little-endian처럼 보이게 하는 PowerPC Little-Endian 지원. Data format은 이 mode 밖의 agent가 접근하기에 부적합 |
`PPC_FEATURE_ICACHE_SNOOP`에서 instruction storage를 data storage와 일치시키는 sequence는 POWER9 Processor User's Manual 4.6.2.2의 `icbi` 설명과 같습니다.
sync
icbi (to any address)
isync`AT_HWCAP2` flag
178-232| Flag | 의미 |
|---|---|
| `PPC_FEATURE2_ARCH_2_07` | v2.07 user-level architecture 지원. 이후 architecture도 set |
| `PPC_FEATURE2_HTM` | Transactional Memory feature 사용 가능 |
| `PPC_FEATURE2_DSCR` | DSCR facility 사용 가능 |
| `PPC_FEATURE2_EBB` | EBB facility 사용 가능 |
| `PPC_FEATURE2_ISEL` | `isel` instruction 사용 가능. `ARCH_2_07` 이상이 대체 |
| `PPC_FEATURE2_TAR` | TAR facility 사용 가능 |
| `PPC_FEATURE2_VEC_CRYPTO` | v2.07 crypto instruction 사용 가능 |
| `PPC_FEATURE2_HTM_NOSC` | Transactional state에서 system call이 실패함. `Documentation/arch/powerpc/syscall64-abi.rst` 참조 |
| `PPC_FEATURE2_ARCH_3_00` | v3.0B/v3.0C user-level architecture 지원. 이후 architecture도 set |
| `PPC_FEATURE2_HAS_IEEE128` | VSX quad-precision instruction/data type으로 IEEE 128-bit binary floating point 지원 |
| `PPC_FEATURE2_DARN` | `darn` instruction 사용 가능 |
| `PPC_FEATURE2_SCV` | `scv 0` instruction을 system call에 사용 가능. `Documentation/arch/powerpc/syscall64-abi.rst` 참조 |
| `PPC_FEATURE2_HTM_NO_SUSPEND` | Suspend를 지원하지 않는 제한된 Transactional Memory facility. `Documentation/arch/powerpc/transactional_memory.rst` 참조 |
| `PPC_FEATURE2_ARCH_3_1` | v3.1 user-level architecture 지원. 이후 architecture도 set |
| `PPC_FEATURE2_MMA` | MMA facility 사용 가능 |
요약과 해설
elf_hwcaps.rst:1-232Userspace는 optional hardware feature를 직접 probe하지 않고 auxiliary vector의 HWCAP bit로 확인해야 합니다. Facility availability와 정확한 ISA-version semantics를 함께 해석해야 합니다.