요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
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===================================================
2
Scalable Vector Extension support for AArch64 Linux
3
===================================================
5
Author: Dave Martin <Dave.Martin@arm.com>
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Date: 4 August 2017
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This document outlines briefly the interface provided to userspace by Linux in
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order to support use of the ARM Scalable Vector Extension (SVE), including
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interactions with Streaming SVE mode added by the Scalable Matrix Extension
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(SME).
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This is an outline of the most important features and issues only and not
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intended to be exhaustive.
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This document does not aim to describe the SVE architecture or programmer's
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model. To aid understanding, a minimal description of relevant programmer's
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model features for SVE is included in Appendix A.
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1. General
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-----------
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* SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
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tracked per-thread.
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* In streaming mode FFR is not accessible unless HWCAP2_SME_FA64 is present
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in the system, when it is not supported and these interfaces are used to
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access streaming mode FFR is read and written as zero.
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* The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
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AT_HWCAP entry. Presence of this flag implies the presence of the SVE
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instructions and registers, and the Linux-specific system interfaces
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described in this document. SVE is reported in /proc/cpuinfo as "sve".
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* Support for the execution of SVE instructions in userspace can also be
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detected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRS
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instruction, and checking that the value of the SVE field is nonzero. [3]
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It does not guarantee the presence of the system interfaces described in the
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following sections: software that needs to verify that those interfaces are
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present must check for HWCAP_SVE instead.
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* On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also
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be reported in the AT_HWCAP2 aux vector entry. In addition to this,
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optional extensions to SVE2 may be reported by the presence of:
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HWCAP2_SVE2
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HWCAP2_SVEAES
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HWCAP2_SVEPMULL
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HWCAP2_SVEBITPERM
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HWCAP2_SVESHA3
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HWCAP2_SVESM4
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HWCAP2_SVE2P1
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This list may be extended over time as the SVE architecture evolves.
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These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1,
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which userspace can read using an MRS instruction. See elf_hwcaps.txt and
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cpu-feature-registers.txt for details.
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* On hardware that supports the SME extensions, HWCAP2_SME will also be
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reported in the AT_HWCAP2 aux vector entry. Among other things SME adds
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streaming mode which provides a subset of the SVE feature set using a
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separate SME vector length and the same Z/V registers. See sme.rst
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for more details.
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* Debuggers should restrict themselves to interacting with the target via the
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NT_ARM_SVE regset. The recommended way of detecting support for this regset
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is to connect to a target process first and then attempt a
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ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov). Note that when SME is
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present and streaming SVE mode is in use the FPSIMD subset of registers
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will be read via NT_ARM_SVE and NT_ARM_SVE writes will exit streaming mode
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in the target.
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* Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory
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between userspace and the kernel, the register value is encoded in memory in
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an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
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byte offset i from the start of the memory representation. This affects for
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example the signal frame (struct sve_context) and ptrace interface
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(struct user_sve_header) and associated data.
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Beware that on big-endian systems this results in a different byte order than
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for the FPSIMD V-registers, which are stored as single host-endian 128-bit
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values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
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byte offset i. (struct fpsimd_context, struct user_fpsimd_state).
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2. Vector length terminology
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-----------------------------
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The size of an SVE vector (Z) register is referred to as the "vector length".
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To avoid confusion about the units used to express vector length, the kernel
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adopts the following conventions:
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* Vector length (VL) = size of a Z-register in bytes
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* Vector quadwords (VQ) = size of a Z-register in units of 128 bits
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(So, VL = 16 * VQ.)
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The VQ convention is used where the underlying granularity is important, such
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as in data structure definitions. In most other situations, the VL convention
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is used. This is consistent with the meaning of the "VL" pseudo-register in
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the SVE instruction set architecture.
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3. System call behaviour
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-------------------------
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* On syscall, V0..V31 are preserved (as without SVE). Thus, bits [127:0] of
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Z0..Z31 are preserved. All other bits of Z0..Z31, and all of P0..P15 and FFR
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become zero on return from a syscall.
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* The SVE registers are not used to pass arguments to or receive results from
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any syscall.
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* All other SVE state of a thread, including the currently configured vector
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length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector
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length (if any), is preserved across all syscalls, subject to the specific
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exceptions for execve() described in section 6.
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In particular, on return from a fork() or clone(), the parent and new child
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process or thread share identical SVE configuration, matching that of the
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parent before the call.
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4. Signal handling
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-------------------
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* A new signal frame record sve_context encodes the SVE registers on signal
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delivery. [1]
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* This record is supplementary to fpsimd_context. The FPSR and FPCR registers
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are only present in fpsimd_context. For convenience, the content of V0..V31
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is duplicated between sve_context and fpsimd_context.
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* The record contains a flag field which includes a flag SVE_SIG_FLAG_SM which
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if set indicates that the thread is in streaming mode and the vector length
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and register data (if present) describe the streaming SVE data and vector
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length.
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* The signal frame record for SVE always contains basic metadata, in particular
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the thread's vector length (in sve_context.vl).
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* The SVE registers may or may not be included in the record, depending on
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whether the registers are live for the thread. The registers are present if
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and only if:
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sve_context.head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)).
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* If the registers are present, the remainder of the record has a vl-dependent
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size and layout. Macros SVE_SIG_* are defined [1] to facilitate access to
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the members.
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* Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
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layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the
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start of the register's representation in memory.
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* If the SVE context is too big to fit in sigcontext.__reserved[], then extra
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space is allocated on the stack, an extra_context record is written in
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__reserved[] referencing this space. sve_context is then written in the
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extra space. Refer to [1] for further details about this mechanism.
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5. Signal return
168
-----------------
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When returning from a signal handler:
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* If there is no sve_context record in the signal frame, or if the record is
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present but contains no register data as described in the previous section,
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then the SVE registers/bits become non-live and take unspecified values.
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* If sve_context is present in the signal frame and contains full register
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data, the SVE registers become live and are populated with the specified
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data. However, for backward compatibility reasons, bits [127:0] of Z0..Z31
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are always restored from the corresponding members of fpsimd_context.vregs[]
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and not from sve_context. The remaining bits are restored from sve_context.
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* Inclusion of fpsimd_context in the signal frame remains mandatory,
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irrespective of whether sve_context is present or not.
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* The vector length cannot be changed via signal return. If sve_context.vl in
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the signal frame does not match the current vector length, the signal return
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attempt is treated as illegal, resulting in a forced SIGSEGV.
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* It is permitted to enter or leave streaming mode by setting or clearing
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the SVE_SIG_FLAG_SM flag but applications should take care to ensure that
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when doing so sve_context.vl and any register data are appropriate for the
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vector length in the new mode.
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6. prctl extensions
196
--------------------
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Some new prctl() calls are added to allow programs to manage the SVE vector
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length:
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prctl(PR_SVE_SET_VL, unsigned long arg)
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Sets the vector length of the calling thread and related flags, where
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arg == vl | flags. Other threads of the calling process are unaffected.
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vl is the desired vector length, where sve_vl_valid(vl) must be true.
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flags:
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PR_SVE_VL_INHERIT
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Inherit the current vector length across execve(). Otherwise, the
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vector length is reset to the system default at execve(). (See
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Section 9.)
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PR_SVE_SET_VL_ONEXEC
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Defer the requested vector length change until the next execve()
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performed by this thread.
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The effect is equivalent to implicit execution of the following
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call immediately after the next execve() (if any) by the thread:
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prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)
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This allows launching of a new program with a different vector
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length, while avoiding runtime side effects in the caller.
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Without PR_SVE_SET_VL_ONEXEC, the requested change takes effect
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immediately.
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Return value: a nonnegative on success, or a negative value on error:
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EINVAL: SVE not supported, invalid vector length requested, or
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invalid flags.
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On success:
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* Either the calling thread's vector length or the deferred vector length
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to be applied at the next execve() by the thread (dependent on whether
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PR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest value
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supported by the system that is less than or equal to vl. If vl ==
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SVE_VL_MAX, the value set will be the largest value supported by the
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system.
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* Any previously outstanding deferred vector length change in the calling
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thread is cancelled.
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* The returned value describes the resulting configuration, encoded as for
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PR_SVE_GET_VL. The vector length reported in this value is the new
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current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not
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present in arg; otherwise, the reported vector length is the deferred
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vector length that will be applied at the next execve() by the calling
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thread.
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* Changing the vector length causes all of P0..P15, FFR and all bits of
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Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
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unspecified. Calling PR_SVE_SET_VL with vl equal to the thread's current
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vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
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flag, does not constitute a change to the vector length for this purpose.
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prctl(PR_SVE_GET_VL)
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Gets the vector length of the calling thread.
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The following flag may be OR-ed into the result:
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PR_SVE_VL_INHERIT
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Vector length will be inherited across execve().
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There is no way to determine whether there is an outstanding deferred
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vector length change (which would only normally be the case between a
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fork() or vfork() and the corresponding execve() in typical use).
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To extract the vector length from the result, bitwise and it with
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PR_SVE_VL_LEN_MASK.
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Return value: a nonnegative value on success, or a negative value on error:
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EINVAL: SVE not supported.
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7. ptrace extensions
287
---------------------
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* New regsets NT_ARM_SVE and NT_ARM_SSVE are defined for use with
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PTRACE_GETREGSET and PTRACE_SETREGSET. NT_ARM_SSVE describes the
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streaming mode SVE registers and NT_ARM_SVE describes the
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non-streaming mode SVE registers.
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In this description a register set is referred to as being "live" when
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the target is in the appropriate streaming or non-streaming mode and is
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using data beyond the subset shared with the FPSIMD Vn registers.
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Refer to [2] for definitions.
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The regset data starts with struct user_sve_header, containing:
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size
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Size of the complete regset, in bytes.
305
This depends on vl and possibly on other things in the future.
307
If a call to PTRACE_GETREGSET requests less data than the value of
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size, the caller can allocate a larger buffer and retry in order to
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read the complete regset.
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max_size
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Maximum size in bytes that the regset can grow to for the target
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thread. The regset won't grow bigger than this even if the target
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thread changes its vector length etc.
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vl
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Target thread's current vector length, in bytes.
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max_vl
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Maximum possible vector length for the target thread.
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flags
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at most one of
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SVE_PT_REGS_FPSIMD
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SVE registers are not live (GETREGSET) or are to be made
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non-live (SETREGSET).
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The payload is of type struct user_fpsimd_state, with the same
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meaning as for NT_PRFPREG, starting at offset
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SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.
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Extra data might be appended in the future: the size of the
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payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).
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vq should be obtained using sve_vq_from_vl(vl).
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or
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SVE_PT_REGS_SVE
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SVE registers are live (GETREGSET) or are to be made live
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(SETREGSET).
350
The payload contains the SVE register data, starting at offset
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SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
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size SVE_PT_SVE_SIZE(vq, flags);
354
... OR-ed with zero or more of the following flags, which have the same
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meaning and behaviour as the corresponding PR_SET_VL_* flags:
357
SVE_PT_VL_INHERIT
359
SVE_PT_VL_ONEXEC (SETREGSET only).
361
If neither FPSIMD nor SVE flags are provided then no register
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payload is available, this is only possible when SME is implemented.
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* The effects of changing the vector length and/or flags are equivalent to
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those documented for PR_SVE_SET_VL.
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The caller must make a further GETREGSET call if it needs to know what VL is
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actually set by SETREGSET, unless is it known in advance that the requested
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VL is supported.
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* In the SVE_PT_REGS_SVE case, the size and layout of the payload depends on
373
the header fields. The SVE_PT_SVE_*() macros are provided to facilitate
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access to the members.
376
* In either case, for SETREGSET it is permissible to omit the payload, in which
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case only the vector length and flags are changed (along with any
378
consequences of those changes).
380
* In systems supporting SME when in streaming mode a GETREGSET for
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NT_REG_SVE will return only the user_sve_header with no register data,
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similarly a GETREGSET for NT_REG_SSVE will not return any register data
383
when not in streaming mode.
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* A GETREGSET for NT_ARM_SSVE will never return SVE_PT_REGS_FPSIMD.
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* For SETREGSET, if an SVE_PT_REGS_SVE payload is present and the
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requested VL is not supported, the effect will be the same as if the
389
payload were omitted, except that an EIO error is reported. No
390
attempt is made to translate the payload data to the correct layout
391
for the vector length actually set. The thread's FPSIMD state is
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preserved, but the remaining bits of the SVE registers become
393
unspecified. It is up to the caller to translate the payload layout
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for the actual VL and retry.
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* Where SME is implemented it is not possible to GETREGSET the register
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state for normal SVE when in streaming mode, nor the streaming mode
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register state when in normal mode, regardless of the implementation defined
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behaviour of the hardware for sharing data between the two modes.
401
* Any SETREGSET of NT_ARM_SVE will exit streaming mode if the target was in
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streaming mode and any SETREGSET of NT_ARM_SSVE will enter streaming mode
403
if the target was not in streaming mode.
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* If any register data is provided along with SVE_PT_VL_ONEXEC then the
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registers data will be interpreted with the current vector length, not
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the vector length configured for use on exec.
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* The effect of writing a partial, incomplete payload is unspecified.
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8. ELF coredump extensions
413
---------------------------
415
* NT_ARM_SVE and NT_ARM_SSVE notes will be added to each coredump for
416
each thread of the dumped process. The contents will be equivalent to the
417
data that would have been read if a PTRACE_GETREGSET of the corresponding
418
type were executed for each thread when the coredump was generated.
420
9. System runtime configuration
421
--------------------------------
423
* To mitigate the ABI impact of expansion of the signal frame, a policy
424
mechanism is provided for administrators, distro maintainers and developers
425
to set the default vector length for userspace processes:
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/proc/sys/abi/sve_default_vector_length
429
Writing the text representation of an integer to this file sets the system
430
default vector length to the specified value rounded to a supported value
431
using the same rules as for setting vector length via PR_SVE_SET_VL.
433
The result can be determined by reopening the file and reading its
434
contents.
436
At boot, the default vector length is initially set to 64 or the maximum
437
supported vector length, whichever is smaller. This determines the initial
438
vector length of the init process (PID 1).
440
Reading this file returns the current system default vector length.
442
* At every execve() call, the new vector length of the new process is set to
443
the system default vector length, unless
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* PR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the
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calling thread, or
448
* a deferred vector length change is pending, established via the
449
PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).
451
* Modifying the system default vector length does not affect the vector length
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of any existing process or thread that does not make an execve() call.
454
10. Perf extensions
455
--------------------------------
457
* The arm64 specific DWARF standard [5] added the VG (Vector Granule) register
458
at index 46. This register is used for DWARF unwinding when variable length
459
SVE registers are pushed onto the stack.
461
* Its value is equivalent to the current SVE vector length (VL) in bits divided
462
by 64.
464
* The value is included in Perf samples in the regs[46] field if
465
PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set.
467
* The value is the current value at the time the sample was taken, and it can
468
change over time.
470
* If the system doesn't support SVE when perf_event_open is called with these
471
settings, the event will fail to open.
473
Appendix A. SVE programmer's model (informative)
474
=================================================
476
This section provides a minimal description of the additions made by SVE to the
477
ARMv8-A programmer's model that are relevant to this document.
479
Note: This section is for information only and not intended to be complete or
480
to replace any architectural specification.
482
A.1. Registers
483
---------------
485
In A64 state, SVE adds the following:
487
* 32 8VL-bit vector registers Z0..Z31
488
For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.
490
A register write using a Vn register name zeros all bits of the corresponding
491
Zn except for bits [127:0].
493
* 16 VL-bit predicate registers P0..P15
495
* 1 VL-bit special-purpose predicate register FFR (the "first-fault register")
497
* a VL "pseudo-register" that determines the size of each vector register
499
The SVE instruction set architecture provides no way to write VL directly.
500
Instead, it can be modified only by EL1 and above, by writing appropriate
501
system registers.
503
* The value of VL can be configured at runtime by EL1 and above:
504
16 <= VL <= VLmax, where VL must be a multiple of 16.
506
* The maximum vector length is determined by the hardware:
507
16 <= VLmax <= 256.
509
(The SVE architecture specifies 256, but permits future architecture
510
revisions to raise this limit.)
512
* FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
513
operations in a similar way to the way in which they interact with ARMv8
514
floating-point operations::
516
8VL-1 128 0 bit index
517
+---- //// -----------------+
518
Z0 | : V0 |
519
: :
520
Z7 | : V7 |
521
Z8 | : * V8 |
522
: : :
523
Z15 | : *V15 |
524
Z16 | : V16 |
525
: :
526
Z31 | : V31 |
527
+---- //// -----------------+
528
31 0
529
VL-1 0 +-------+
530
+---- //// --+ FPSR | |
531
P0 | | +-------+
532
: | | *FPCR | |
533
P15 | | +-------+
534
+---- //// --+
535
FFR | | +-----+
536
+---- //// --+ VL | |
537
+-----+
539
(*) callee-save:
540
This only applies to bits [63:0] of Z-/V-registers.
541
FPCR contains callee-save and caller-save bits. See [4] for details.
544
A.2. Procedure call standard
545
-----------------------------
547
The ARMv8-A base procedure call standard is extended as follows with respect to
548
the additional SVE register state:
550
* All SVE register bits that are not shared with FP/SIMD are caller-save.
552
* Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.
554
This follows from the way these bits are mapped to V8..V15, which are caller-
555
save in the base procedure call standard.
558
Appendix B. ARMv8-A FP/SIMD programmer's model
559
===============================================
561
Note: This section is for information only and not intended to be complete or
562
to replace any architectural specification.
564
Refer to [4] for more information.
566
ARMv8-A defines the following floating-point / SIMD register state:
568
* 32 128-bit vector registers V0..V31
569
* 2 32-bit status/control registers FPSR, FPCR
571
::
573
127 0 bit index
574
+---------------+
575
V0 | |
576
: : :
577
V7 | |
578
* V8 | |
579
: : : :
580
*V15 | |
581
V16 | |
582
: : :
583
V31 | |
584
+---------------+
586
31 0
587
+-------+
588
FPSR | |
589
+-------+
590
*FPCR | |
591
+-------+
593
(*) callee-save:
594
This only applies to bits [63:0] of V-registers.
595
FPCR contains a mixture of callee-save and caller-save bits.
598
References
599
==========
601
[1] arch/arm64/include/uapi/asm/sigcontext.h
602
AArch64 Linux signal ABI definitions
604
[2] arch/arm64/include/uapi/asm/ptrace.h
605
AArch64 Linux ptrace ABI definitions
607
[3] Documentation/arch/arm64/cpu-feature-registers.rst
609
[4] ARM IHI0055C
610
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
611
http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
612
Procedure Call Standard for the ARM 64-bit Architecture (AArch64)
614
[5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
개요와 일반 규칙
1-89저자: Dave Martin, 2017-08-04. 이 문서는 ARM Scalable Vector Extension(SVE)을 위한 Linux userspace interface와 SME가 추가한 Streaming SVE mode의 상호 작용을 설명합니다. 핵심 feature와 issue의 개요이며 완전한 architecture 설명은 아닙니다. Appendix A에 필요한 최소 programmer's model을 싣습니다.
`Z0..Z31`, `P0..P15`, `FFR`, 현재 vector length `VL`은 thread별로 추적합니다. Streaming mode의 `FFR`은 system에 `HWCAP2_SME_FA64`가 없으면 접근할 수 없으며, interface로 읽거나 쓸 때 0으로 처리합니다.
| 표시 | 보고 경로 | 의미 |
|---|---|---|
| `HWCAP_SVE` | `AT_HWCAP`, `/proc/cpuinfo: sve` | SVE 명령·register와 Linux interface |
| `HWCAP2_SVE2` | `AT_HWCAP2` | SVE2 extension |
| `HWCAP2_SVEAES` | `AT_HWCAP2` | Optional SVE2 extension |
| `HWCAP2_SVEPMULL` | `AT_HWCAP2` | Optional SVE2 extension |
| `HWCAP2_SVEBITPERM` | `AT_HWCAP2` | Optional SVE2 extension |
| `HWCAP2_SVESHA3` | `AT_HWCAP2` | Optional SVE2 extension |
| `HWCAP2_SVESM4` | `AT_HWCAP2` | Optional SVE2 extension |
| `HWCAP2_SVE2P1` | `AT_HWCAP2` | Optional SVE2 extension |
| `ID_AA64ZFR0_EL1` | EL0 `MRS` | Optional SVE extension field |
| `HWCAP2_SME` | `AT_HWCAP2` | 별도 SME vector length를 쓰는 Streaming SVE mode |
`ID_AA64PFR0_EL1.SVE`를 `MRS`로 읽어 nonzero인지 확인하면 명령 실행은 탐지할 수 있지만 Linux interface까지 보장하지 않습니다. Interface 존재는 `HWCAP_SVE`로 확인해야 합니다.
Debugger는 `NT_ARM_SVE` regset을 사용하며 target에 연결한 뒤 `ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov)`를 시도해 지원을 탐지하는 것이 권장됩니다. SME가 있고 target이 streaming mode이면 `NT_ARM_SVE`로 FPSIMD subset을 읽고, `NT_ARM_SVE` write는 target을 streaming mode에서 나오게 합니다.
`Zn`, `Pn`, `FFR`을 memory에서 교환할 때 bit `[(8*i+7):(8*i)]`를 byte offset `i`에 두는 endianness-invariant layout을 사용합니다. Big-endian system의 FPSIMD `V` register는 host-endian 128-bit 값이므로 byte 순서가 다릅니다. 이는 `sve_context`, `user_sve_header`, `fpsimd_context`, `user_fpsimd_state` 해석에 중요합니다.
Vector length 용어
90-109SVE vector(`Z`) register의 크기를 vector length라고 합니다. 단위 혼동을 막기 위해 kernel은 다음 표기를 사용합니다.
| 표기 | 정의 |
|---|---|
| VL | `Z` register size in bytes |
| VQ | `Z` register size in 128-bit units; `VL = 16 * VQ` |
Data structure처럼 underlying granularity가 중요한 곳은 VQ를, 그 밖에는 대체로 VL을 사용합니다. 이는 SVE ISA의 `VL` pseudo-register 의미와 일치합니다.
System call 동작
110-129Syscall에서는 SVE가 없을 때와 마찬가지로 `V0..V31`을 보존하므로 `Z0..Z31`의 `[127:0]`도 보존합니다. 그 밖의 `Z` bit와 `P0..P15`, `FFR`은 syscall return 때 0이 됩니다.
SVE register는 syscall argument나 result 전달에 쓰지 않습니다. 현재 VL, `PR_SVE_VL_INHERIT`, deferred VL 등 나머지 SVE state는 6절의 `execve()` 예외를 빼면 syscall 전반에서 유지됩니다. `fork()` 또는 `clone()` 뒤 parent와 child의 SVE configuration도 call 전 parent와 같습니다.
Signal 전달
130-166Signal 전달 시 새 `struct sve_context` record가 SVE register를 encoding하며 `fpsimd_context`를 보완합니다. `FPSR`와 `FPCR`은 `fpsimd_context`에만 있고, 편의를 위해 `V0..V31` 내용은 두 context에 중복됩니다.
| 항목 | 규칙 |
|---|---|
| `SVE_SIG_FLAG_SM` | 설정되면 thread가 streaming mode이며 record의 VL/data가 Streaming SVE를 설명 |
| `sve_context.vl`과 payload | Metadata는 항상 존재; `head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(vl))`일 때만 register data 존재 |
Payload가 있으면 size와 layout은 VL에 의존하고 `SVE_SIG_*` macro로 접근합니다. 각 `Zn`, `Pn`, `FFR`은 bit `[(8*i+7):(8*i)]`를 byte offset `i`에 두는 endianness-invariant layout입니다.
SVE context가 `sigcontext.__reserved[]`에 들어가지 않으면 stack에 extra space를 할당하고 `extra_context`가 이를 참조하게 한 뒤 그 공간에 `sve_context`를 씁니다.
Signal return
167-194`sve_context`가 없거나 register data가 없으면 SVE register/bit가 non-live가 되고 unspecified 값을 가집니다. Full data가 있으면 SVE register를 live로 만들고 지정 data를 복원합니다.
Backward compatibility 때문에 `Z0..Z31[127:0]`은 `sve_context`가 아니라 대응하는 `fpsimd_context.vregs[]`에서 항상 복원하고 나머지 bit만 `sve_context`에서 복원합니다. `fpsimd_context`는 SVE context 존재와 무관하게 signal frame에 반드시 있어야 합니다.
Signal return으로 VL을 바꿀 수 없습니다. `sve_context.vl`이 현재 VL과 다르면 강제 `SIGSEGV`가 발생합니다. `SVE_SIG_FLAG_SM`을 설정하거나 clear하여 streaming mode에 들어가거나 나오는 것은 허용하지만 새 mode의 VL과 register layout에 맞는 값을 제공해야 합니다.
prctl vector-length 제어
195-285`prctl(PR_SVE_SET_VL, unsigned long arg)`는 calling thread의 VL과 flag를 설정합니다. `arg == vl | flags`이며 다른 thread에는 영향이 없습니다. `vl`은 `sve_vl_valid(vl)`을 만족해야 합니다.
| Flag | 효과 |
|---|---|
| `PR_SVE_VL_INHERIT` | `execve()`에서 현재 VL 상속; 없으면 system default로 reset |
| `PR_SVE_SET_VL_ONEXEC` | 변경을 이 thread의 다음 `execve()` 직후까지 연기 |
`PR_SVE_SET_VL_ONEXEC`은 다음 call을 다음 `execve()` 직후 암묵적으로 실행하는 것과 같습니다.
prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)이 방식은 caller에 runtime side effect를 주지 않고 다른 VL로 새 program을 실행합니다. Flag가 없으면 즉시 변경합니다. 성공은 nonnegative 값, SVE 미지원·invalid VL·invalid flag는 `EINVAL`입니다.
- 현재 또는 deferred VL은 system이 지원하는 값 중 요청값 이하의 가장 큰 값입니다. `vl == SVE_VL_MAX`이면 지원 최대값입니다.
- 기존 deferred VL change를 취소합니다.
- Return value는 `PR_SVE_GET_VL` 형식이며 `ONEXEC` 여부에 따라 현재 또는 deferred VL을 보고합니다.
- 실제 VL이 바뀌면 `P0..P15`, `FFR`, 각 `Z0..Z31`의 `[127:0]` 밖 bit가 unspecified가 됩니다. 현재값과 같은 `vl` 또는 `ONEXEC` 요청은 이 목적에서 변경이 아닙니다.
`prctl(PR_SVE_GET_VL)`은 calling thread의 VL을 반환하고 `PR_SVE_VL_INHERIT`가 OR될 수 있습니다. Deferred change의 존재는 조회할 수 없습니다. 결과와 `PR_SVE_VL_LEN_MASK`를 bitwise AND해 VL을 추출합니다. SVE가 없으면 `EINVAL`입니다.
ptrace regset
286-411`NT_ARM_SVE`와 `NT_ARM_SSVE`는 `PTRACE_GETREGSET`/`PTRACE_SETREGSET`용입니다. 전자는 non-streaming, 후자는 streaming SVE register를 설명합니다. 적절한 mode에서 FPSIMD `Vn`과 공유하지 않는 data를 실제 사용하는 state를 `live`라고 부릅니다.
| `struct user_sve_header` field | 의미 |
|---|---|
| `size` | 현재 complete regset byte size; 작은 buffer를 받으면 확대 후 재시도 |
| `max_size` | Target의 VL이 바뀌어도 regset이 넘지 않는 최대 byte size |
| `vl` | Target의 현재 VL(byte) |
| `max_vl` | Target이 가질 수 있는 최대 VL |
| `flags` | Register payload mode 하나와 선택적 `SVE_PT_VL_*` |
| Flag | Payload와 의미 |
|---|---|
| `SVE_PT_REGS_FPSIMD` | SVE non-live; `SVE_PT_FPSIMD_OFFSET`의 `struct user_fpsimd_state`, size는 `SVE_PT_FPSIMD_SIZE(vq, flags)` |
| `SVE_PT_REGS_SVE` | SVE live; `SVE_PT_SVE_OFFSET`부터 SVE data, size는 `SVE_PT_SVE_SIZE(vq, flags)` |
| Payload flag 없음 | Register payload 없음; SME 구현 system에서만 가능 |
`vq`는 `sve_vq_from_vl(vl)`로 구합니다. `SVE_PT_VL_INHERIT`와 SETREGSET 전용 `SVE_PT_VL_ONEXEC`은 대응 `PR_SET_VL_*`과 같은 의미입니다. VL/flag 변경 효과도 `PR_SVE_SET_VL`과 같고 실제 VL을 모르면 SETREGSET 뒤 GETREGSET으로 확인해야 합니다.
- `SVE_PT_REGS_SVE` payload는 header에 따라 layout이 달라지며 `SVE_PT_SVE_*()` macro를 사용합니다.
- SETREGSET에서 payload를 생략하면 VL과 flag만 바뀝니다.
- Streaming mode에서 `NT_ARM_SVE`, normal mode에서 `NT_ARM_SSVE` GETREGSET은 header만 반환합니다. `NT_ARM_SSVE`는 `SVE_PT_REGS_FPSIMD`를 반환하지 않습니다.
- 지원하지 않는 VL의 SVE payload SETREGSET은 payload 생략과 같은 state change 후 `EIO`를 냅니다. FPSIMD는 보존하고 나머지는 unspecified이며 caller가 실제 VL layout으로 변환해 재시도합니다.
- SME system에서는 현재 mode가 아닌 쪽의 full register state를 GETREGSET할 수 없습니다.
- `NT_ARM_SVE` SETREGSET은 streaming mode에서 나오고 `NT_ARM_SSVE` SETREGSET은 streaming mode로 들어갑니다.
- `SVE_PT_VL_ONEXEC`과 data를 함께 주면 data는 deferred exec VL이 아니라 현재 VL로 해석합니다. Partial payload 효과는 unspecified입니다.
ELF coredump
412-419Dump되는 process의 각 thread마다 `NT_ARM_SVE`와 `NT_ARM_SSVE` note를 추가합니다. 내용은 coredump 생성 시 각 type에 `PTRACE_GETREGSET`을 실행했을 때 읽을 data와 같습니다.
System runtime configuration
420-453Signal frame 확장의 ABI 영향을 줄이기 위해 `/proc/sys/abi/sve_default_vector_length`로 사용자 process의 system default VL을 관리합니다.
정수를 쓰면 `PR_SVE_SET_VL`과 같은 규칙으로 지원 값에 round합니다. File을 다시 열어 결과를 확인할 수 있습니다. Boot 초기값은 64와 지원 최대 VL 중 작은 값이며 init process(PID 1)의 초기 VL이 됩니다. File read는 현재 default를 반환합니다.
각 `execve()`에서 새 process는 system default VL을 받습니다. 단, `PR_SVE_VL_INHERIT`/`SVE_PT_VL_INHERIT`가 있거나 `PR_SVE_SET_VL_ONEXEC`/`SVE_PT_VL_ONEXEC` deferred change가 있으면 예외입니다. Default 변경은 이후 `execve()`를 하지 않는 기존 process/thread에 영향을 주지 않습니다.
Perf extension
454-472Arm64 전용 DWARF 표준은 variable-length SVE register를 stack에 push한 경우 unwind하기 위해 index 46에 `VG`(Vector Granule) register를 추가했습니다.
| 항목 | 값/조건 |
|---|---|
| Register index | `46` |
| `VG` 값 | 현재 SVE `VL`(bits) / 64 |
| Perf sample | `PERF_SAMPLE_REGS_USER`와 `sample_regs_user` bit 46이 모두 설정되면 `regs[46]` |
| SVE 미지원 | 이 설정으로 `perf_event_open()`하면 event open 실패 |
Sample 시점의 현재값이므로 시간에 따라 바뀔 수 있습니다.
Appendix A: SVE programmer's model
473-557이 appendix는 ARMv8-A programmer's model에 SVE가 추가한 최소 사항만 설명하며 architecture specification을 대체하지 않습니다.
| Register/state | 크기 | Alias와 제어 |
|---|---|---|
| `Z0..Z31` | 각 `8VL` bits | `Zn[127:0]`은 `Vn`; `Vn` write는 대응 `Zn`의 나머지 bit를 zero |
| `P0..P15` | 각 `VL` bits | Predicate register |
| `FFR` | `VL` bits | First-fault predicate register |
| `VL` | 16..VLmax bytes, 16의 배수 | EL1 이상만 system register로 변경 |
| `VLmax` | 16..256 bytes | Hardware가 결정; 향후 architecture는 상한을 늘릴 수 있음 |
원문의 ASCII register 그림은 위 표와 아래 저장 규칙으로 구조화했습니다. `FPSR`와 `FPCR`은 ARMv8-A에서 유지되며 SVE floating-point operation과 상호 작용합니다.
| Procedure-call state | 보존 규칙 |
|---|---|
| FP/SIMD와 공유하지 않는 모든 SVE bit | Caller-save |
| `Z8[63:0]..Z15[63:0]` | Base PCS의 `V8..V15` mapping에 따라 callee-save |
Callee-save 표시는 `Z`/`V` register의 `[63:0]`에만 적용됩니다. `FPCR`에는 callee-save와 caller-save bit가 섞여 있습니다.
Appendix B와 참고 자료
558-614Appendix B는 ARMv8-A FP/SIMD programmer's model의 정보용 요약이며 specification을 대체하지 않습니다. 자세한 내용은 reference [4]를 참조합니다.
| FP/SIMD state | 크기와 보존 |
|---|---|
| `V0..V31` | 각 128 bits; `V8..V15[63:0]`만 callee-save |
| `FPSR`, `FPCR` | 각 32 bits; `FPCR`은 callee-save와 caller-save bit 혼합 |
원문의 두 번째 ASCII 그림은 이 표로 다시 그렸습니다. SVE의 `Z` register low 128 bits가 이 `V` register와 alias한다는 점이 두 appendix를 연결합니다.
| Reference | 내용 |
|---|---|
| `arch/arm64/include/uapi/asm/sigcontext.h` | AArch64 Linux signal ABI |
| `arch/arm64/include/uapi/asm/ptrace.h` | AArch64 Linux ptrace ABI |
| `Documentation/arch/arm64/cpu-feature-registers.rst` | CPU feature register interface |
| `ARM IHI0055C` | AArch64 Procedure Call Standard |
| AArch64 DWARF | `https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst` |
요약과 해설
sve.rst:1-614SVE는 thread마다 가변 폭의 `Z`, `P`, `FFR` state를 가집니다. Linux는 VL에 따라 달라지는 frame과 regset layout을 header와 macro로 기술하고, `Z[127:0]`과 기존 `V` register의 alias를 유지해 이전 FP/SIMD ABI와 호환합니다.
Register가 kernel 경계를 통과하면서 보존되거나 non-live가 되는 흐름입니다.
두 ASCII diagram의 register 폭, alias, 보존 관계를 하나의 표로 다시 그렸습니다.