요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
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===================================================================
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Marvell Odyssey DDR PMU Performance Monitoring Unit (PMU UNCORE)
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===================================================================
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Odyssey DRAM Subsystem supports eight counters for monitoring performance
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and software can program those counters to monitor any of the defined
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performance events. Supported performance events include those counted
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at the interface between the DDR controller and the PHY, interface between
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the DDR Controller and the CHI interconnect, or within the DDR Controller.
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Additionally DSS also supports two fixed performance event counters, one
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for ddr reads and the other for ddr writes.
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The counter will be operating in either manual or auto mode.
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The PMU driver exposes the available events and format options under sysfs::
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/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/events/
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/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/format/
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Examples::
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$ perf list | grep ddr
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mrvl_ddr_pmu_<>/ddr_act_bypass_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_bsm_alloc/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_bsm_starvation/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_active_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_mwr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_rd_active_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_rd_or_wr_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_read/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_wr_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_cam_write/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_capar_error/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_crit_ref/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_ddr_reads/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_ddr_writes/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_cmd_is_retry/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_cycles/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_parity_poison/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_rd_data_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dfi_wr_data_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dqsosc_mpc/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_dqsosc_mrr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_enter_mpsm/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_enter_powerdown/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_enter_selfref/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_pri_rdaccess/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_rd_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_rd_or_wr_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_rmw_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hif_wr_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_hpri_sched_rd_crit_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_load_mode/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_lpri_sched_rd_crit_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_precharge/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_precharge_for_other/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_precharge_for_rdwr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_raw_hazard/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_rd_bypass_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_rd_crc_error/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_rd_uc_ecc_error/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_rdwr_transitions/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_refresh/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_retry_fifo_full/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_spec_ref/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_tcr_mrr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_war_hazard/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_waw_hazard/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_win_limit_reached_rd/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_win_limit_reached_wr/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_wr_crc_error/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_wr_trxn_crit_access/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_write_combine/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_zqcl/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_zqlatch/ [Kernel PMU event]
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mrvl_ddr_pmu_<>/ddr_zqstart/ [Kernel PMU event]
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$ perf stat -e ddr_cam_read,ddr_cam_write,ddr_cam_active_access,ddr_cam
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rd_or_wr_access,ddr_cam_rd_active_access,ddr_cam_mwr <workload>
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
DSS programmable와 fixed counters
1-14Marvell Odyssey DRAM Subsystem은 performance monitoring용 counter 8개를 제공하며, software가 정의된 performance events 중 하나를 각 counter에 program할 수 있습니다.
Event는 DDR controller와 PHY 사이, DDR Controller와 CHI interconnect 사이, 또는 DDR Controller 내부에서 셉니다.
DSS에는 `ddr reads`와 `ddr writes`를 위한 fixed performance event counter도 각각 하나씩 있습니다. Counter는 manual mode 또는 auto mode로 동작합니다.
Event와 format discovery
15-20PMU driver는 사용 가능한 event와 format option을 sysfs에 노출합니다.
/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/events/
/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/format/| 항목 | 경로 |
|---|---|
| Events | `/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/events/` |
| Format | `/sys/bus/event_source/devices/mrvl_ddr_pmu_<>/format/` |
DDR event 목록과 perf stat
21-80`perf list | grep ddr`로 PMU instance의 전체 kernel PMU event를 확인하고, 필요한 CAM read/write와 active access event를 한 `perf stat` 명령에 묶습니다.
$ perf list | grep ddr
mrvl_ddr_pmu_<>/ddr_act_bypass_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_bsm_alloc/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_bsm_starvation/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_active_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_mwr/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_rd_active_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_rd_or_wr_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_read/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_wr_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_cam_write/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_capar_error/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_crit_ref/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_ddr_reads/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_ddr_writes/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_cmd_is_retry/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_cycles/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_parity_poison/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_rd_data_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dfi_wr_data_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dqsosc_mpc/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_dqsosc_mrr/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_enter_mpsm/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_enter_powerdown/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_enter_selfref/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_pri_rdaccess/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_rd_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_rd_or_wr_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_rmw_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hif_wr_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_hpri_sched_rd_crit_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_load_mode/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_lpri_sched_rd_crit_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_precharge/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_precharge_for_other/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_precharge_for_rdwr/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_raw_hazard/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rd_bypass_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rd_crc_error/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rd_uc_ecc_error/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_rdwr_transitions/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_refresh/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_retry_fifo_full/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_spec_ref/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_tcr_mrr/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_war_hazard/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_waw_hazard/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_win_limit_reached_rd/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_win_limit_reached_wr/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_wr_crc_error/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_wr_trxn_crit_access/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_write_combine/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_zqcl/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_zqlatch/ [Kernel PMU event]
mrvl_ddr_pmu_<>/ddr_zqstart/ [Kernel PMU event]
$ perf stat -e ddr_cam_read,ddr_cam_write,ddr_cam_active_access,ddr_cam
rd_or_wr_access,ddr_cam_rd_active_access,ddr_cam_mwr <workload>| 기능군 | 관찰 내용 |
|---|---|
| CAM/BSM | Allocation, starvation, active/read/write access |
| DDR/DFI | Fixed reads/writes, cycles, command retry, data access |
| Power/mode | MPSM, powerdown, self-refresh, load mode |
| HIF/scheduler | Read/write access와 high/low priority critical read |
| Hazard | RAW, WAR, WAW, read/write transition |
| Error/retry | Parity poison, CRC, uncorrected ECC, retry FIFO |
| Precharge/window | Precharge 원인과 read/write window limit |
| Refresh/calibration | Refresh, speculative/critical refresh, ZQ/MRR |
영역대표 event
CAM`ddr_cam_read`, `ddr_cam_write`, `ddr_cam_active_access`
DFI`ddr_dfi_cycles`, `ddr_dfi_rd_data_access`, `ddr_dfi_wr_data_access`
HIF`ddr_hif_rd_access`, `ddr_hif_wr_access`, `ddr_hif_rmw_access`
Hazard`ddr_raw_hazard`, `ddr_war_hazard`, `ddr_waw_hazard`
Power`ddr_enter_mpsm`, `ddr_enter_powerdown`, `ddr_enter_selfref`
Error`ddr_rd_crc_error`, `ddr_wr_crc_error`, `ddr_rd_uc_ecc_error`
Refresh`ddr_refresh`, `ddr_crit_ref`, `ddr_spec_ref`
Calibration`ddr_zqcl`, `ddr_zqlatch`, `ddr_zqstart`
긴 `perf list` 출력을 counter가 관찰하는 DDR Controller 동작별로 구조화했습니다.
운영 요약
mrvl-odyssey-ddr-pmu.rst:1-80DSS의 8 programmable counter와 read/write fixed counter에서 DDR-PHY, DDR-CHI, controller 내부 event를 골라 manual 또는 auto mode로 측정합니다.