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Linux 6.18.37 · Administration / Performance

Alibaba T-Head SoC Uncore PMU

Yitian 710 DDR Driveway PMU의 topology, counter group, HIF bandwidth event와 제약을 설명합니다.

Source pathDocumentation/admin-guide/perf/alibaba_pmu.rst
Source versionLinux v6.18.37
TranslationDUJINLABS 전문 번역 + 해설

요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.

1. 요약·해설

원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.

운영 핵심

alibaba_pmu.rst:1-105

Sub-channel별 PMU 이름과 event를 확인하고 `perf stat`으로 HIF command를 집계해 DRAM bandwidth를 계산합니다.

관점핵심
SoCAlibaba T-Head Yitian 710
TopologyDie당 4개, 총 8개 DDR5/4 channel; DDR5 channel당 2 sub-channel
PMU 이름`ali_drw_<sys_base_addr>`
CounterSub-channel당 36개, 현재 driver는 Group 0과 Group 3 사용
Bandwidth event`hif_rd`, `hif_wr`, `hif_rmw`, `cycle`
제한Sampling, `perf record`, task attach 미지원

2. 영어 원문 전체

번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.

원문 전체 펼치기
1 =============================================================
2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
3 =============================================================
4
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
7 facilitate system maintenance.
8
9 DDR Sub-System Driveway (DRW) PMU Driver
10 =========================================
11
12 Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
13 is independent of others to service system memory requests. And one DDR5
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
16 metrics.
17
18 The Driveway PMU devices are named as ali_drw_<sys_base_addr> with perf.
19 For example, ali_drw_21000 and ali_drw_21080 are two PMU devices for two
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
21 prefixed with ali_drw_400XXXXX, e.g. ali_drw_40021000.
22
23 Each sub-channel has 36 PMU counters in total, which is classified into
24 four groups:
25
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
27 pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
28 based on DDRC core clock.
29
30 - Group 1: PMU Bandwidth Counters. This group has 8 counters that are used
31 to count the total access number of either the eight bank groups in a
32 selected rank, or four ranks separately in the first 4 counters. The base
33 transfer unit is 64B.
34
35 - Group 2: PMU Retry Counters. This group has 10 counters, that intend to
36 count the total retry number of each type of uncorrectable error.
37
38 - Group 3: PMU Common Counters. This group has 16 counters, that are used
39 to count the common events.
40
41 For now, the Driveway PMU driver only uses counters in group 0 and group 3.
42
43 The DDR Controller (DDRCTL) and DDR PHY combine to create a complete solution
44 for connecting an SoC application bus to DDR memory devices. The DDRCTL
45 receives transactions Host Interface (HIF) which is custom-defined by Synopsys.
46 These transactions are queued internally and scheduled for access while
47 satisfying the SDRAM protocol timing requirements, transaction priorities, and
48 dependencies between the transactions. The DDRCTL in turn issues commands on
49 the DDR PHY Interface (DFI) to the PHY module, which launches and captures data
50 to and from the SDRAM. The driveway PMUs have hardware logic to gather
51 statistics and performance logging signals on HIF, DFI, etc.
52
53 By counting the READ, WRITE and RMW commands sent to the DDRC through the HIF
54 interface, we could calculate the bandwidth. Example usage of counting memory
55 data bandwidth::
56
57 perf stat \
58 -e ali_drw_21000/hif_wr/ \
59 -e ali_drw_21000/hif_rd/ \
60 -e ali_drw_21000/hif_rmw/ \
61 -e ali_drw_21000/cycle/ \
62 -e ali_drw_21080/hif_wr/ \
63 -e ali_drw_21080/hif_rd/ \
64 -e ali_drw_21080/hif_rmw/ \
65 -e ali_drw_21080/cycle/ \
66 -e ali_drw_23000/hif_wr/ \
67 -e ali_drw_23000/hif_rd/ \
68 -e ali_drw_23000/hif_rmw/ \
69 -e ali_drw_23000/cycle/ \
70 -e ali_drw_23080/hif_wr/ \
71 -e ali_drw_23080/hif_rd/ \
72 -e ali_drw_23080/hif_rmw/ \
73 -e ali_drw_23080/cycle/ \
74 -e ali_drw_25000/hif_wr/ \
75 -e ali_drw_25000/hif_rd/ \
76 -e ali_drw_25000/hif_rmw/ \
77 -e ali_drw_25000/cycle/ \
78 -e ali_drw_25080/hif_wr/ \
79 -e ali_drw_25080/hif_rd/ \
80 -e ali_drw_25080/hif_rmw/ \
81 -e ali_drw_25080/cycle/ \
82 -e ali_drw_27000/hif_wr/ \
83 -e ali_drw_27000/hif_rd/ \
84 -e ali_drw_27000/hif_rmw/ \
85 -e ali_drw_27000/cycle/ \
86 -e ali_drw_27080/hif_wr/ \
87 -e ali_drw_27080/hif_rd/ \
88 -e ali_drw_27080/hif_rmw/ \
89 -e ali_drw_27080/cycle/ -- sleep 10
90
91 Example usage of counting all memory read/write bandwidth by metric::
92
93 perf stat -M ddr_read_bandwidth.all -- sleep 10
94 perf stat -M ddr_write_bandwidth.all -- sleep 10
95
96 The average DRAM bandwidth can be calculated as follows:
97
98 - Read Bandwidth = perf_hif_rd * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle
99 - Write Bandwidth = (perf_hif_wr + perf_hif_rmw) * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle
100
101 Here, DDRC_WIDTH = 64 bytes.
102
103 The current driver does not support sampling. So "perf record" is
104 unsupported. Also attach to a task is unsupported as the events are all
105 uncore.
106

3. 한국어 전문 번역

영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.

Yitian 710 uncore PMU

1-8

`Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)` 문서는 Alibaba Group의 chip-development business인 T-Head가 자체 제작한 Yitian 710의 uncore PMU를 설명합니다.

이 PMU는 performance와 functional debugging을 제공해 system maintenance를 돕습니다.

DDR Sub-System Driveway와 counter group

9-41

`DDR Sub-System Driveway (DRW) PMU Driver`가 다루는 Yitian 710에는 DDR5/4 channel이 8개 있으며 die마다 4개씩 배치됩니다. 각 DDR5 channel은 다른 channel과 독립적으로 system memory request를 처리하고, 다시 독립된 sub-channel 두 개로 나뉩니다.

DDR Sub-System Driveway는 여러 performance metric을 monitoring하기 위해 sub-channel마다 별도 PMU를 구현합니다.

Perf에서 Driveway PMU device 이름은 `ali_drw_<sys_base_addr>` 형식입니다. 예를 들어 `ali_drw_21000`과 `ali_drw_21080`은 die 0의 같은 channel에 속한 두 sub-channel PMU입니다. Die 1 PMU에는 `ali_drw_400XXXXX` prefix가 붙으며 예시는 `ali_drw_40021000`입니다.

각 sub-channel에는 총 `36 PMU counters`가 있고 네 group으로 분류됩니다.

Group이름Counter 수역할
Group 0PMU Cycle Counter2`pmu_cycle_cnt_low`, `pmu_cycle_cnt_high`; DDRC core clock 기준 cycle count
Group 1PMU Bandwidth Counters8선택 rank의 8 bank group 전체 access 또는 앞 4 counter에서 4개 rank별 access; 64B transfer unit
Group 2PMU Retry Counters10각 uncorrectable error type의 전체 retry 수
Group 3PMU Common Counters16Common event count

현재 Driveway PMU driver는 Group 0과 Group 3의 counter만 사용합니다.

DDRCTL·HIF·DFI data path

42-55

`DDR Controller (DDRCTL)`와 `DDR PHY`는 SoC application bus를 DDR memory device에 연결하는 완전한 solution을 구성합니다.

DDRCTL은 Synopsys가 custom-defined한 `Host Interface (HIF)` transaction을 받습니다. Transaction은 내부 queue에 들어가며 SDRAM protocol timing requirements, transaction priority와 transaction 사이 dependency를 만족하도록 access 순서가 scheduling됩니다.

DDRCTL은 `DDR PHY Interface (DFI)`로 PHY module에 command를 보내고, PHY가 SDRAM과 주고받는 data를 launch하고 capture합니다. Driveway PMU hardware logic은 HIF, DFI 등의 statistics와 performance logging signal을 수집합니다.

Yitian 710 DDR command와 data 경로
SoC application busHost Interface (HIF)DDR Controller (DDRCTL)DDR PHY Interface (DFI)PHY moduleSDRAM

Host transaction이 DDRCTL scheduling과 DFI를 거쳐 PHY·SDRAM으로 이동하고 Driveway PMU가 HIF·DFI signal을 집계하는 구조입니다.

HIF를 통해 DDRC로 보낸 `READ`, `WRITE`, `RMW` command를 세면 bandwidth를 계산할 수 있습니다.

perf stat 예시와 bandwidth 공식

56-101

다음 명령은 die 0의 여러 Driveway sub-channel에서 `hif_wr`, `hif_rd`, `hif_rmw`, `cycle` event를 10초 동안 함께 측정합니다.

perf stat \
  -e ali_drw_21000/hif_wr/ \
  -e ali_drw_21000/hif_rd/ \
  -e ali_drw_21000/hif_rmw/ \
  -e ali_drw_21000/cycle/ \
  -e ali_drw_21080/hif_wr/ \
  -e ali_drw_21080/hif_rd/ \
  -e ali_drw_21080/hif_rmw/ \
  -e ali_drw_21080/cycle/ \
  -e ali_drw_23000/hif_wr/ \
  -e ali_drw_23000/hif_rd/ \
  -e ali_drw_23000/hif_rmw/ \
  -e ali_drw_23000/cycle/ \
  -e ali_drw_23080/hif_wr/ \
  -e ali_drw_23080/hif_rd/ \
  -e ali_drw_23080/hif_rmw/ \
  -e ali_drw_23080/cycle/ \
  -e ali_drw_25000/hif_wr/ \
  -e ali_drw_25000/hif_rd/ \
  -e ali_drw_25000/hif_rmw/ \
  -e ali_drw_25000/cycle/ \
  -e ali_drw_25080/hif_wr/ \
  -e ali_drw_25080/hif_rd/ \
  -e ali_drw_25080/hif_rmw/ \
  -e ali_drw_25080/cycle/ \
  -e ali_drw_27000/hif_wr/ \
  -e ali_drw_27000/hif_rd/ \
  -e ali_drw_27000/hif_rmw/ \
  -e ali_drw_27000/cycle/ \
  -e ali_drw_27080/hif_wr/ \
  -e ali_drw_27080/hif_rd/ \
  -e ali_drw_27080/hif_rmw/ \
  -e ali_drw_27080/cycle/ -- sleep 10

모든 memory read/write bandwidth는 metric으로도 집계할 수 있습니다.

perf stat -M ddr_read_bandwidth.all -- sleep 10
perf stat -M ddr_write_bandwidth.all -- sleep 10

Average DRAM bandwidth 계산식은 다음과 같습니다.

Metric공식
Read Bandwidth`perf_hif_rd * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle`
Write Bandwidth`(perf_hif_wr + perf_hif_rmw) * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle`

여기서 `DDRC_WIDTH = 64 bytes`입니다.

Sampling과 task attach 제한

102-105

현재 driver는 sampling을 지원하지 않으므로 `perf record`는 unsupported입니다.

모든 event가 uncore event이므로 특정 task에 attach하는 기능도 지원하지 않습니다.