요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.
1. 요약·해설
원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.
2. 영어 원문 전체
번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.
원문 전체 펼치기
.. SPDX-License-Identifier: GPL-2.0
.. include:: <isonum.txt>
==================================================
Reliability, Availability and Serviceability (RAS)
==================================================
This documents different aspects of the RAS functionality present in the
kernel.
RAS concepts
************
Reliability, Availability and Serviceability (RAS) is a concept used on
servers meant to measure their robustness.
Reliability
is the probability that a system will produce correct outputs.
* Generally measured as Mean Time Between Failures (MTBF)
* Enhanced by features that help to avoid, detect and repair hardware faults
Availability
is the probability that a system is operational at a given time
* Generally measured as a percentage of downtime per a period of time
* Often uses mechanisms to detect and correct hardware faults in
runtime;
Serviceability (or maintainability)
is the simplicity and speed with which a system can be repaired or
maintained
* Generally measured on Mean Time Between Repair (MTBR)
Improving RAS
-------------
In order to reduce systems downtime, a system should be capable of detecting
hardware errors, and, when possible correcting them in runtime. It should
also provide mechanisms to detect hardware degradation, in order to warn
the system administrator to take the action of replacing a component before
it causes data loss or system downtime.
Among the monitoring measures, the most usual ones include:
* CPU – detect errors at instruction execution and at L1/L2/L3 caches;
* Memory – add error correction logic (ECC) to detect and correct errors;
* I/O – add CRC checksums for transferred data;
* Storage – RAID, journal file systems, checksums,
Self-Monitoring, Analysis and Reporting Technology (SMART).
By monitoring the number of occurrences of error detections, it is possible
to identify if the probability of hardware errors is increasing, and, on such
case, do a preventive maintenance to replace a degraded component while
those errors are correctable.
Types of errors
---------------
Most mechanisms used on modern systems use technologies like Hamming
Codes that allow error correction when the number of errors on a bit packet
is below a threshold. If the number of errors is above, those mechanisms
can indicate with a high degree of confidence that an error happened, but
they can't correct.
Also, sometimes an error occur on a component that it is not used. For
example, a part of the memory that it is not currently allocated.
That defines some categories of errors:
* **Correctable Error (CE)** - the error detection mechanism detected and
corrected the error. Such errors are usually not fatal, although some
Kernel mechanisms allow the system administrator to consider them as fatal.
* **Uncorrected Error (UE)** - the amount of errors happened above the error
correction threshold, and the system was unable to auto-correct.
* **Fatal Error** - when an UE error happens on a critical component of the
system (for example, a piece of the Kernel got corrupted by an UE), the
only reliable way to avoid data corruption is to hang or reboot the machine.
* **Non-fatal Error** - when an UE error happens on an unused component,
like a CPU in power down state or an unused memory bank, the system may
still run, eventually replacing the affected hardware by a hot spare,
if available.
Also, when an error happens on a userspace process, it is also possible to
kill such process and let userspace restart it.
The mechanism for handling non-fatal errors is usually complex and may
require the help of some userspace application, in order to apply the
policy desired by the system administrator.
Identifying a bad hardware component
------------------------------------
Just detecting a hardware flaw is usually not enough, as the system needs
to pinpoint to the minimal replaceable unit (MRU) that should be exchanged
to make the hardware reliable again.
So, it requires not only error logging facilities, but also mechanisms that
will translate the error message to the silkscreen or component label for
the MRU.
Typically, it is very complex for memory, as modern CPUs interlace memory
from different memory modules, in order to provide a better performance. The
DMI BIOS usually have a list of memory module labels, with can be obtained
using the ``dmidecode`` tool. For example, on a desktop machine, it shows::
Memory Device
Total Width: 64 bits
Data Width: 64 bits
Size: 16384 MB
Form Factor: SODIMM
Set: None
Locator: ChannelA-DIMM0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 2133 MHz
Rank: 2
Configured Clock Speed: 2133 MHz
On the above example, a DDR4 SO-DIMM memory module is located at the
system's memory labeled as "BANK 0", as given by the *bank locator* field.
Please notice that, on such system, the *total width* is equal to the
*data width*. It means that such memory module doesn't have error
detection/correction mechanisms.
Unfortunately, not all systems use the same field to specify the memory
bank. On this example, from an older server, ``dmidecode`` shows::
Memory Device
Array Handle: 0x1000
Error Information Handle: Not Provided
Total Width: 72 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: DIMM
Set: 1
Locator: DIMM_A1
Bank Locator: Not Specified
Type: DDR3
Type Detail: Synchronous Registered (Buffered)
Speed: 1600 MHz
Rank: 2
Configured Clock Speed: 1600 MHz
There, the DDR3 RDIMM memory module is located at the system's memory labeled
as "DIMM_A1", as given by the *locator* field. Please notice that this
memory module has 64 bits of *data width* and 72 bits of *total width*. So,
it has 8 extra bits to be used by error detection and correction mechanisms.
Such kind of memory is called Error-correcting code memory (ECC memory).
To make things even worse, it is not uncommon that systems with different
labels on their system's board to use exactly the same BIOS, meaning that
the labels provided by the BIOS won't match the real ones.
ECC memory
----------
As mentioned in the previous section, ECC memory has extra bits to be
used for error correction. In the above example, a memory module has
64 bits of *data width*, and 72 bits of *total width*. The extra 8
bits which are used for the error detection and correction mechanisms
are referred to as the *syndrome*\ [#f1]_\ [#f2]_.
So, when the cpu requests the memory controller to write a word with
*data width*, the memory controller calculates the *syndrome* in real time,
using Hamming code, or some other error correction code, like SECDED+,
producing a code with *total width* size. Such code is then written
on the memory modules.
At read, the *total width* bits code is converted back, using the same
ECC code used on write, producing a word with *data width* and a *syndrome*.
The word with *data width* is sent to the CPU, even when errors happen.
The memory controller also looks at the *syndrome* in order to check if
there was an error, and if the ECC code was able to fix such error.
If the error was corrected, a Corrected Error (CE) happened. If not, an
Uncorrected Error (UE) happened.
The information about the CE/UE errors is stored on some special registers
at the memory controller and can be accessed by reading such registers,
either by BIOS, by some special CPUs or by Linux EDAC driver. On x86 64
bit CPUs, such errors can also be retrieved via the Machine Check
Architecture (MCA)\ [#f3]_.
.. [#f1] Please notice that several memory controllers allow operation on a
mode called "Lock-Step", where it groups two memory modules together,
doing 128-bit reads/writes. That gives 16 bits for error correction, with
significantly improves the error correction mechanism, at the expense
that, when an error happens, there's no way to know what memory module is
to blame. So, it has to blame both memory modules.
.. [#f2] Some memory controllers also allow using memory in mirror mode.
On such mode, the same data is written to two memory modules. At read,
the system checks both memory modules, in order to check if both provide
identical data. On such configuration, when an error happens, there's no
way to know what memory module is to blame. So, it has to blame both
memory modules (or 4 memory modules, if the system is also on Lock-step
mode).
.. [#f3] For more details about the Machine Check Architecture (MCA),
please read Documentation/arch/x86/x86_64/machinecheck.rst at the Kernel tree.
EDAC - Error Detection And Correction
*************************************
.. note::
"bluesmoke" was the name for this device driver subsystem when it
was "out-of-tree" and maintained at http://bluesmoke.sourceforge.net.
That site is mostly archaic now and can be used only for historical
purposes.
When the subsystem was pushed upstream for the first time, on
Kernel 2.6.16, it was renamed to ``EDAC``.
Purpose
-------
The ``edac`` kernel module's goal is to detect and report hardware errors
that occur within the computer system running under linux.
Memory
------
Memory Correctable Errors (CE) and Uncorrectable Errors (UE) are the
primary errors being harvested. These types of errors are harvested by
the ``edac_mc`` device.
Detecting CE events, then harvesting those events and reporting them,
**can** but must not necessarily be a predictor of future UE events. With
CE events only, the system can and will continue to operate as no data
has been damaged yet.
However, preventive maintenance and proactive part replacement of memory
modules exhibiting CEs can reduce the likelihood of the dreaded UE events
and system panics.
Other hardware elements
-----------------------
A new feature for EDAC, the ``edac_device`` class of device, was added in
the 2.6.23 version of the kernel.
This new device type allows for non-memory type of ECC hardware detectors
to have their states harvested and presented to userspace via the sysfs
interface.
Some architectures have ECC detectors for L1, L2 and L3 caches,
along with DMA engines, fabric switches, main data path switches,
interconnections, and various other hardware data paths. If the hardware
reports it, then an edac_device device probably can be constructed to
harvest and present that to userspace.
PCI bus scanning
----------------
In addition, PCI devices are scanned for PCI Bus Parity and SERR Errors
in order to determine if errors are occurring during data transfers.
The presence of PCI Parity errors must be examined with a grain of salt.
There are several add-in adapters that do **not** follow the PCI specification
with regards to Parity generation and reporting. The specification says
the vendor should tie the parity status bits to 0 if they do not intend
to generate parity. Some vendors do not do this, and thus the parity bit
can "float" giving false positives.
There is a PCI device attribute located in sysfs that is checked by
the EDAC PCI scanning code. If that attribute is set, PCI parity/error
scanning is skipped for that device. The attribute is::
broken_parity_status
and is located in ``/sys/devices/pci<XXX>/0000:XX:YY.Z`` directories for
PCI devices.
Versioning
----------
EDAC is composed of a "core" module (``edac_core.ko``) and several Memory
Controller (MC) driver modules. On a given system, the CORE is loaded
and one MC driver will be loaded. Both the CORE and the MC driver (or
``edac_device`` driver) have individual versions that reflect current
release level of their respective modules.
Thus, to "report" on what version a system is running, one must report
both the CORE's and the MC driver's versions.
Loading
-------
If ``edac`` was statically linked with the kernel then no loading
is necessary. If ``edac`` was built as modules then simply modprobe
the ``edac`` pieces that you need. You should be able to modprobe
hardware-specific modules and have the dependencies load the necessary
core modules.
Example::
$ modprobe amd76x_edac
loads both the ``amd76x_edac.ko`` memory controller module and the
``edac_mc.ko`` core module.
Sysfs interface
---------------
EDAC presents a ``sysfs`` interface for control and reporting purposes. It
lives in the /sys/devices/system/edac directory.
Within this directory there currently reside 2 components:
======= ==============================
mc memory controller(s) system
pci PCI control and status system
======= ==============================
Memory Controller (mc) Model
----------------------------
Each ``mc`` device controls a set of memory modules [#f4]_. These modules
are laid out in a Chip-Select Row (``csrowX``) and Channel table (``chX``).
There can be multiple csrows and multiple channels.
.. [#f4] Nowadays, the term DIMM (Dual In-line Memory Module) is widely
used to refer to a memory module, although there are other memory
packaging alternatives, like SO-DIMM, SIMM, etc. The UEFI
specification (Version 2.7) defines a memory module in the Common
Platform Error Record (CPER) section to be an SMBIOS Memory Device
(Type 17). Along this document, and inside the EDAC subsystem, the term
"dimm" is used for all memory modules, even when they use a
different kind of packaging.
Memory controllers allow for several csrows, with 8 csrows being a
typical value. Yet, the actual number of csrows depends on the layout of
a given motherboard, memory controller and memory module characteristics.
Dual channels allow for dual data length (e. g. 128 bits, on 64 bit systems)
data transfers to/from the CPU from/to memory. Some newer chipsets allow
for more than 2 channels, like Fully Buffered DIMMs (FB-DIMMs) memory
controllers. The following example will assume 2 channels:
+------------+-----------------------+
| CS Rows | Channels |
+------------+-----------+-----------+
| | ``ch0`` | ``ch1`` |
+============+===========+===========+
| |**DIMM_A0**|**DIMM_B0**|
+------------+-----------+-----------+
| ``csrow0`` | rank0 | rank0 |
+------------+-----------+-----------+
| ``csrow1`` | rank1 | rank1 |
+------------+-----------+-----------+
| |**DIMM_A1**|**DIMM_B1**|
+------------+-----------+-----------+
| ``csrow2`` | rank0 | rank0 |
+------------+-----------+-----------+
| ``csrow3`` | rank1 | rank1 |
+------------+-----------+-----------+
In the above example, there are 4 physical slots on the motherboard
for memory DIMMs:
+---------+---------+
| DIMM_A0 | DIMM_B0 |
+---------+---------+
| DIMM_A1 | DIMM_B1 |
+---------+---------+
Labels for these slots are usually silk-screened on the motherboard.
Slots labeled ``A`` are channel 0 in this example. Slots labeled ``B`` are
channel 1. Notice that there are two csrows possible on a physical DIMM.
These csrows are allocated their csrow assignment based on the slot into
which the memory DIMM is placed. Thus, when 1 DIMM is placed in each
Channel, the csrows cross both DIMMs.
Memory DIMMs come single or dual "ranked". A rank is a populated csrow.
In the example above 2 dual ranked DIMMs are similarly placed. Thus,
both csrow0 and csrow1 are populated. On the other hand, when 2 single
ranked DIMMs are placed in slots DIMM_A0 and DIMM_B0, then they will
have just one csrow (csrow0) and csrow1 will be empty. The pattern
repeats itself for csrow2 and csrow3. Also note that some memory
controllers don't have any logic to identify the memory module, see
``rankX`` directories below.
The representation of the above is reflected in the directory
tree in EDAC's sysfs interface. Starting in directory
``/sys/devices/system/edac/mc``, each memory controller will be
represented by its own ``mcX`` directory, where ``X`` is the
index of the MC::
..../edac/mc/
|
|->mc0
|->mc1
|->mc2
....
Under each ``mcX`` directory each ``csrowX`` is again represented by a
``csrowX``, where ``X`` is the csrow index::
.../mc/mc0/
|
|->csrow0
|->csrow2
|->csrow3
....
Notice that there is no csrow1, which indicates that csrow0 is composed
of a single ranked DIMMs. This should also apply in both Channels, in
order to have dual-channel mode be operational. Since both csrow2 and
csrow3 are populated, this indicates a dual ranked set of DIMMs for
channels 0 and 1.
Within each of the ``mcX`` and ``csrowX`` directories are several EDAC
control and attribute files.
``mcX`` directories
-------------------
In ``mcX`` directories are EDAC control and attribute files for
this ``X`` instance of the memory controllers.
For a description of the sysfs API, please see:
Documentation/ABI/testing/sysfs-devices-edac
``dimmX`` or ``rankX`` directories
----------------------------------
The recommended way to use the EDAC subsystem is to look at the information
provided by the ``dimmX`` or ``rankX`` directories [#f5]_.
A typical EDAC system has the following structure under
``/sys/devices/system/edac/``\ [#f6]_::
/sys/devices/system/edac/
├── mc
│ ├── mc0
│ │ ├── ce_count
│ │ ├── ce_noinfo_count
│ │ ├── dimm0
│ │ │ ├── dimm_ce_count
│ │ │ ├── dimm_dev_type
│ │ │ ├── dimm_edac_mode
│ │ │ ├── dimm_label
│ │ │ ├── dimm_location
│ │ │ ├── dimm_mem_type
│ │ │ ├── dimm_ue_count
│ │ │ ├── size
│ │ │ └── uevent
│ │ ├── max_location
│ │ ├── mc_name
│ │ ├── reset_counters
│ │ ├── seconds_since_reset
│ │ ├── size_mb
│ │ ├── ue_count
│ │ ├── ue_noinfo_count
│ │ └── uevent
│ ├── mc1
│ │ ├── ce_count
│ │ ├── ce_noinfo_count
│ │ ├── dimm0
│ │ │ ├── dimm_ce_count
│ │ │ ├── dimm_dev_type
│ │ │ ├── dimm_edac_mode
│ │ │ ├── dimm_label
│ │ │ ├── dimm_location
│ │ │ ├── dimm_mem_type
│ │ │ ├── dimm_ue_count
│ │ │ ├── size
│ │ │ └── uevent
│ │ ├── max_location
│ │ ├── mc_name
│ │ ├── reset_counters
│ │ ├── seconds_since_reset
│ │ ├── size_mb
│ │ ├── ue_count
│ │ ├── ue_noinfo_count
│ │ └── uevent
│ └── uevent
└── uevent
In the ``dimmX`` directories are EDAC control and attribute files for
this ``X`` memory module:
- ``size`` - Total memory managed by this csrow attribute file
This attribute file displays, in count of megabytes, the memory
that this csrow contains.
- ``dimm_ue_count`` - Uncorrectable Errors count attribute file
This attribute file displays the total count of uncorrectable
errors that have occurred on this DIMM. If panic_on_ue is set
this counter will not have a chance to increment, since EDAC
will panic the system.
- ``dimm_ce_count`` - Correctable Errors count attribute file
This attribute file displays the total count of correctable
errors that have occurred on this DIMM. This count is very
important to examine. CEs provide early indications that a
DIMM is beginning to fail. This count field should be
monitored for non-zero values and report such information
to the system administrator.
- ``dimm_dev_type`` - Device type attribute file
This attribute file will display what type of DRAM device is
being utilized on this DIMM.
Examples:
- x1
- x2
- x4
- x8
- ``dimm_edac_mode`` - EDAC Mode of operation attribute file
This attribute file will display what type of Error detection
and correction is being utilized.
- ``dimm_label`` - memory module label control file
This control file allows this DIMM to have a label assigned
to it. With this label in the module, when errors occur
the output can provide the DIMM label in the system log.
This becomes vital for panic events to isolate the
cause of the UE event.
DIMM Labels must be assigned after booting, with information
that correctly identifies the physical slot with its
silk screen label. This information is currently very
motherboard specific and determination of this information
must occur in userland at this time.
- ``dimm_location`` - location of the memory module
The location can have up to 3 levels, and describe how the
memory controller identifies the location of a memory module.
Depending on the type of memory and memory controller, it
can be:
- *csrow* and *channel* - used when the memory controller
doesn't identify a single DIMM - e. g. in ``rankX`` dir;
- *branch*, *channel*, *slot* - typically used on FB-DIMM memory
controllers;
- *channel*, *slot* - used on Nehalem and newer Intel drivers.
- ``dimm_mem_type`` - Memory Type attribute file
This attribute file will display what type of memory is currently
on this csrow. Normally, either buffered or unbuffered memory.
Examples:
- Registered-DDR
- Unbuffered-DDR
.. [#f5] On some systems, the memory controller doesn't have any logic
to identify the memory module. On such systems, the directory is called ``rankX`` and works on a similar way as the ``csrowX`` directories.
On modern Intel memory controllers, the memory controller identifies the
memory modules directly. On such systems, the directory is called ``dimmX``.
.. [#f6] There are also some ``power`` directories and ``subsystem``
symlinks inside the sysfs mapping that are automatically created by
the sysfs subsystem. Currently, they serve no purpose.
``csrowX`` directories
----------------------
When CONFIG_EDAC_LEGACY_SYSFS is enabled, sysfs will contain the ``csrowX``
directories. As this API doesn't work properly for Rambus, FB-DIMMs and
modern Intel Memory Controllers, this is being deprecated in favor of
``dimmX`` directories.
In the ``csrowX`` directories are EDAC control and attribute files for
this ``X`` instance of csrow:
- ``ue_count`` - Total Uncorrectable Errors count attribute file
This attribute file displays the total count of uncorrectable
errors that have occurred on this csrow. If panic_on_ue is set
this counter will not have a chance to increment, since EDAC
will panic the system.
- ``ce_count`` - Total Correctable Errors count attribute file
This attribute file displays the total count of correctable
errors that have occurred on this csrow. This count is very
important to examine. CEs provide early indications that a
DIMM is beginning to fail. This count field should be
monitored for non-zero values and report such information
to the system administrator.
- ``size_mb`` - Total memory managed by this csrow attribute file
This attribute file displays, in count of megabytes, the memory
that this csrow contains.
- ``mem_type`` - Memory Type attribute file
This attribute file will display what type of memory is currently
on this csrow. Normally, either buffered or unbuffered memory.
Examples:
- Registered-DDR
- Unbuffered-DDR
- ``edac_mode`` - EDAC Mode of operation attribute file
This attribute file will display what type of Error detection
and correction is being utilized.
- ``dev_type`` - Device type attribute file
This attribute file will display what type of DRAM device is
being utilized on this DIMM.
Examples:
- x1
- x2
- x4
- x8
- ``ch0_ce_count`` - Channel 0 CE Count attribute file
This attribute file will display the count of CEs on this
DIMM located in channel 0.
- ``ch0_ue_count`` - Channel 0 UE Count attribute file
This attribute file will display the count of UEs on this
DIMM located in channel 0.
- ``ch0_dimm_label`` - Channel 0 DIMM Label control file
This control file allows this DIMM to have a label assigned
to it. With this label in the module, when errors occur
the output can provide the DIMM label in the system log.
This becomes vital for panic events to isolate the
cause of the UE event.
DIMM Labels must be assigned after booting, with information
that correctly identifies the physical slot with its
silk screen label. This information is currently very
motherboard specific and determination of this information
must occur in userland at this time.
- ``ch1_ce_count`` - Channel 1 CE Count attribute file
This attribute file will display the count of CEs on this
DIMM located in channel 1.
- ``ch1_ue_count`` - Channel 1 UE Count attribute file
This attribute file will display the count of UEs on this
DIMM located in channel 0.
- ``ch1_dimm_label`` - Channel 1 DIMM Label control file
This control file allows this DIMM to have a label assigned
to it. With this label in the module, when errors occur
the output can provide the DIMM label in the system log.
This becomes vital for panic events to isolate the
cause of the UE event.
DIMM Labels must be assigned after booting, with information
that correctly identifies the physical slot with its
silk screen label. This information is currently very
motherboard specific and determination of this information
must occur in userland at this time.
System Logging
--------------
If logging for UEs and CEs is enabled, then system logs will contain
information indicating that errors have been detected::
EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, channel 1 "DIMM_B1": amd76x_edac
EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0, channel 1 "DIMM_B1": amd76x_edac
The structure of the message is:
+---------------------------------------+-------------+
| Content | Example |
+=======================================+=============+
| The memory controller | MC0 |
+---------------------------------------+-------------+
| Error type | CE |
+---------------------------------------+-------------+
| Memory page | 0x283 |
+---------------------------------------+-------------+
| Offset in the page | 0xce0 |
+---------------------------------------+-------------+
| The byte granularity | grain 8 |
| or resolution of the error | |
+---------------------------------------+-------------+
| The error syndrome | 0xb741 |
+---------------------------------------+-------------+
| Memory row | row 0 |
+---------------------------------------+-------------+
| Memory channel | channel 1 |
+---------------------------------------+-------------+
| DIMM label, if set prior | DIMM B1 |
+---------------------------------------+-------------+
| And then an optional, driver-specific | |
| message that may have additional | |
| information. | |
+---------------------------------------+-------------+
Both UEs and CEs with no info will lack all but memory controller, error
type, a notice of "no info" and then an optional, driver-specific error
message.
PCI Bus Parity Detection
------------------------
On Header Type 00 devices, the primary status is looked at for any
parity error regardless of whether parity is enabled on the device or
not. (The spec indicates parity is generated in some cases). On Header
Type 01 bridges, the secondary status register is also looked at to see
if parity occurred on the bus on the other side of the bridge.
Sysfs configuration
-------------------
Under ``/sys/devices/system/edac/pci`` are control and attribute files as
follows:
- ``check_pci_parity`` - Enable/Disable PCI Parity checking control file
This control file enables or disables the PCI Bus Parity scanning
operation. Writing a 1 to this file enables the scanning. Writing
a 0 to this file disables the scanning.
Enable::
echo "1" >/sys/devices/system/edac/pci/check_pci_parity
Disable::
echo "0" >/sys/devices/system/edac/pci/check_pci_parity
- ``pci_parity_count`` - Parity Count
This attribute file will display the number of parity errors that
have been detected.
Module parameters
-----------------
- ``edac_mc_panic_on_ue`` - Panic on UE control file
An uncorrectable error will cause a machine panic. This is usually
desirable. It is a bad idea to continue when an uncorrectable error
occurs - it is indeterminate what was uncorrected and the operating
system context might be so mangled that continuing will lead to further
corruption. If the kernel has MCE configured, then EDAC will never
notice the UE.
LOAD TIME::
module/kernel parameter: edac_mc_panic_on_ue=[0|1]
RUN TIME::
echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue
- ``edac_mc_log_ue`` - Log UE control file
Generate kernel messages describing uncorrectable errors. These errors
are reported through the system message log system. UE statistics
will be accumulated even when UE logging is disabled.
LOAD TIME::
module/kernel parameter: edac_mc_log_ue=[0|1]
RUN TIME::
echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue
- ``edac_mc_log_ce`` - Log CE control file
Generate kernel messages describing correctable errors. These
errors are reported through the system message log system.
CE statistics will be accumulated even when CE logging is disabled.
LOAD TIME::
module/kernel parameter: edac_mc_log_ce=[0|1]
RUN TIME::
echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce
- ``edac_mc_poll_msec`` - Polling period control file
The time period, in milliseconds, for polling for error information.
Too small a value wastes resources. Too large a value might delay
necessary handling of errors and might loose valuable information for
locating the error. 1000 milliseconds (once each second) is the current
default. Systems which require all the bandwidth they can get, may
increase this.
LOAD TIME::
module/kernel parameter: edac_mc_poll_msec=[0|1]
RUN TIME::
echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec
- ``panic_on_pci_parity`` - Panic on PCI PARITY Error
This control file enables or disables panicking when a parity
error has been detected.
module/kernel parameter::
edac_panic_on_pci_pe=[0|1]
Enable::
echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
Disable::
echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
EDAC device type
----------------
In the header file, edac_pci.h, there is a series of edac_device structures
and APIs for the EDAC_DEVICE.
User space access to an edac_device is through the sysfs interface.
At the location ``/sys/devices/system/edac`` (sysfs) new edac_device devices
will appear.
There is a three level tree beneath the above ``edac`` directory. For example,
the ``test_device_edac`` device (found at the http://bluesmoke.sourceforget.net
website) installs itself as::
/sys/devices/system/edac/test-instance
in this directory are various controls, a symlink and one or more ``instance``
directories.
The standard default controls are:
============== =======================================================
log_ce boolean to log CE events
log_ue boolean to log UE events
panic_on_ue boolean to ``panic`` the system if an UE is encountered
(default off, can be set true via startup script)
poll_msec time period between POLL cycles for events
============== =======================================================
The test_device_edac device adds at least one of its own custom control:
============== ==================================================
test_bits which in the current test driver does nothing but
show how it is installed. A ported driver can
add one or more such controls and/or attributes
for specific uses.
One out-of-tree driver uses controls here to allow
for ERROR INJECTION operations to hardware
injection registers
============== ==================================================
The symlink points to the 'struct dev' that is registered for this edac_device.
Instances
---------
One or more instance directories are present. For the ``test_device_edac``
case:
+----------------+
| test-instance0 |
+----------------+
In this directory there are two default counter attributes, which are totals of
counter in deeper subdirectories.
============== ====================================
ce_count total of CE events of subdirectories
ue_count total of UE events of subdirectories
============== ====================================
Blocks
------
At the lowest directory level is the ``block`` directory. There can be 0, 1
or more blocks specified in each instance:
+-------------+
| test-block0 |
+-------------+
In this directory the default attributes are:
============== ================================================
ce_count which is counter of CE events for this ``block``
of hardware being monitored
ue_count which is counter of UE events for this ``block``
of hardware being monitored
============== ================================================
The ``test_device_edac`` device adds 4 attributes and 1 control:
================== ====================================================
test-block-bits-0 for every POLL cycle this counter
is incremented
test-block-bits-1 every 10 cycles, this counter is bumped once,
and test-block-bits-0 is set to 0
test-block-bits-2 every 100 cycles, this counter is bumped once,
and test-block-bits-1 is set to 0
test-block-bits-3 every 1000 cycles, this counter is bumped once,
and test-block-bits-2 is set to 0
================== ====================================================
================== ====================================================
reset-counters writing ANY thing to this control will
reset all the above counters.
================== ====================================================
Use of the ``test_device_edac`` driver should enable any others to create their own
unique drivers for their hardware systems.
The ``test_device_edac`` sample driver is located at the
http://bluesmoke.sourceforge.net project site for EDAC.
Usage of EDAC APIs on Nehalem and newer Intel CPUs
--------------------------------------------------
On older Intel architectures, the memory controller was part of the North
Bridge chipset. Nehalem, Sandy Bridge, Ivy Bridge, Haswell, Sky Lake and
newer Intel architectures integrated an enhanced version of the memory
controller (MC) inside the CPUs.
This chapter will cover the differences of the enhanced memory controllers
found on newer Intel CPUs, such as ``i7core_edac``, ``sb_edac`` and
``sbx_edac`` drivers.
.. note::
The Xeon E7 processor families use a separate chip for the memory
controller, called Intel Scalable Memory Buffer. This section doesn't
apply for such families.
1) There is one Memory Controller per Quick Patch Interconnect
(QPI). At the driver, the term "socket" means one QPI. This is
associated with a physical CPU socket.
Each MC have 3 physical read channels, 3 physical write channels and
3 logic channels. The driver currently sees it as just 3 channels.
Each channel can have up to 3 DIMMs.
The minimum known unity is DIMMs. There are no information about csrows.
As EDAC API maps the minimum unity is csrows, the driver sequentially
maps channel/DIMM into different csrows.
For example, supposing the following layout::
Ch0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs
dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400
Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs
dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs
dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
The driver will map it as::
csrow0: channel 0, dimm0
csrow1: channel 0, dimm1
csrow2: channel 1, dimm0
csrow3: channel 2, dimm0
exports one DIMM per csrow.
Each QPI is exported as a different memory controller.
2) The MC has the ability to inject errors to test drivers. The drivers
implement this functionality via some error injection nodes:
For injecting a memory error, there are some sysfs nodes, under
``/sys/devices/system/edac/mc/mc?/``:
- ``inject_addrmatch/*``:
Controls the error injection mask register. It is possible to specify
several characteristics of the address to match an error code::
dimm = the affected dimm. Numbers are relative to a channel;
rank = the memory rank;
channel = the channel that will generate an error;
bank = the affected bank;
page = the page address;
column (or col) = the address column.
each of the above values can be set to "any" to match any valid value.
At driver init, all values are set to any.
For example, to generate an error at rank 1 of dimm 2, for any channel,
any bank, any page, any column::
echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank
To return to the default behaviour of matching any, you can do::
echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank
- ``inject_eccmask``:
specifies what bits will have troubles,
- ``inject_section``:
specifies what ECC cache section will get the error::
3 for both
2 for the highest
1 for the lowest
- ``inject_type``:
specifies the type of error, being a combination of the following bits::
bit 0 - repeat
bit 1 - ecc
bit 2 - parity
- ``inject_enable``:
starts the error generation when something different than 0 is written.
All inject vars can be read. root permission is needed for write.
Datasheet states that the error will only be generated after a write on an
address that matches inject_addrmatch. It seems, however, that reading will
also produce an error.
For example, the following code will generate an error for any write access
at socket 0, on any DIMM/address on channel 2::
echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel
echo 2 >/sys/devices/system/edac/mc/mc0/inject_type
echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask
echo 3 >/sys/devices/system/edac/mc/mc0/inject_section
echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable
dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null
For socket 1, it is needed to replace "mc0" by "mc1" at the above
commands.
The generated error message will look like::
EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error))
3) Corrected Error memory register counters
Those newer MCs have some registers to count memory errors. The driver
uses those registers to report Corrected Errors on devices with Registered
DIMMs.
However, those counters don't work with Unregistered DIMM. As the chipset
offers some counters that also work with UDIMMs (but with a worse level of
granularity than the default ones), the driver exposes those registers for
UDIMM memories.
They can be read by looking at the contents of ``all_channel_counts/``::
$ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0
0
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1
0
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2
0
What happens here is that errors on different csrows, but at the same
dimm number will increment the same counter.
So, in this memory mapping::
csrow0: channel 0, dimm0
csrow1: channel 0, dimm1
csrow2: channel 1, dimm0
csrow3: channel 2, dimm0
The hardware will increment udimm0 for an error at the first dimm at either
csrow0, csrow2 or csrow3;
The hardware will increment udimm1 for an error at the second dimm at either
csrow0, csrow2 or csrow3;
The hardware will increment udimm2 for an error at the third dimm at either
csrow0, csrow2 or csrow3;
4) Standard error counters
The standard error counters are generated when an mcelog error is received
by the driver. Since, with UDIMM, this is counted by software, it is
possible that some errors could be lost. With RDIMM's, they display the
contents of the registers
Reference documents used on ``amd64_edac``
------------------------------------------
``amd64_edac`` module is based on the following documents
(available from http://support.amd.com/en-us/search/tech-docs):
1. :Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
Opteron Processors
:AMD publication #: 26094
:Revision: 3.26
:Link: http://support.amd.com/TechDocs/26094.PDF
2. :Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
Processors
:AMD publication #: 32559
:Revision: 3.00
:Issue Date: May 2006
:Link: http://support.amd.com/TechDocs/32559.pdf
3. :Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
Processors
:AMD publication #: 31116
:Revision: 3.00
:Issue Date: September 07, 2007
:Link: http://support.amd.com/TechDocs/31116.pdf
4. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
Models 30h-3Fh Processors
:AMD publication #: 49125
:Revision: 3.06
:Issue Date: 2/12/2015 (latest release)
:Link: http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
5. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
Models 60h-6Fh Processors
:AMD publication #: 50742
:Revision: 3.01
:Issue Date: 7/23/2015 (latest release)
:Link: http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf
6. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 16h
Models 00h-0Fh Processors
:AMD publication #: 48751
:Revision: 3.03
:Issue Date: 2/23/2015 (latest release)
:Link: http://support.amd.com/TechDocs/48751_16h_bkdg.pdf
Credits
=======
* Written by Doug Thompson <dougthompson@xmission.com>
- 7 Dec 2005
- 17 Jul 2007 Updated
* |copy| Mauro Carvalho Chehab
- 05 Aug 2009 Nehalem interface
- 26 Oct 2016 Converted to ReST and cleanups at the Nehalem section
* EDAC authors/maintainers:
- Doug Thompson, Dave Jiang, Dave Peterson et al,
- Mauro Carvalho Chehab
- Borislav Petkov
- original author: Thayne Harbaugh
3. 한국어 전문 번역
영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.
RAS 개념, 개선 방법, 오류 유형
1-94이 `GPL-2.0` 문서는 kernel에 있는 Reliability, Availability and Serviceability(RAS) 기능의 여러 측면을 설명하며 `isonum.txt`를 include합니다.
RAS는 server의 견고성을 측정하는 개념입니다. Reliability는 system이 올바른 output을 낼 확률이며 보통 Mean Time Between Failures(MTBF)로 측정합니다. Hardware fault를 예방·검출·수리하는 기능이 reliability를 높입니다.
Availability는 주어진 시점에 system이 가동 중일 확률입니다. 일정 기간의 downtime 비율로 측정하며, runtime hardware fault 검출·수정 mechanism을 자주 사용합니다.
Serviceability 또는 maintainability는 system을 수리하거나 유지보수할 때의 단순성과 속도입니다. 원문은 이를 Mean Time Between Repair(MTBR)로 측정한다고 설명합니다.
Downtime을 줄이려면 hardware error를 감지하고 가능하면 runtime에 수정해야 합니다. Hardware degradation도 감지해 data loss나 downtime 전에 system administrator가 component를 교체하도록 경고해야 합니다.
일반적인 monitoring은 CPU instruction execution과 L1/L2/L3 cache error, memory ECC, I/O 전송 data의 CRC checksum, storage의 RAID·journal filesystem·checksum·SMART를 포함합니다.
Error 검출 횟수를 관찰하면 hardware error 확률이 증가하는지 판단할 수 있습니다. 아직 수정 가능한 단계에서 성능이 저하된 component를 예방 정비로 교체할 수 있습니다.
현대 system의 Hamming Code 같은 기술은 bit packet의 error 수가 threshold보다 적을 때 수정할 수 있습니다. Threshold를 넘으면 error 발생을 높은 신뢰도로 알 수 있지만 수정할 수는 없습니다. 현재 할당되지 않은 memory처럼 사용하지 않는 component에서도 error가 날 수 있습니다.
Correctable Error(CE)는 검출 mechanism이 찾아 수정한 오류입니다. 보통 fatal하지 않지만 kernel policy에 따라 fatal로 취급할 수 있습니다. Uncorrected Error(UE)는 오류 수가 correction threshold를 넘어 system이 자동 수정하지 못한 경우입니다.
Critical component에서 UE가 발생해 kernel 일부가 손상된 경우 data corruption을 피하는 신뢰할 수 있는 방법은 machine을 멈추거나 reboot하는 것입니다. 이를 Fatal Error라고 합니다.
Power-down CPU나 사용하지 않는 memory bank에서 UE가 난 Non-fatal Error라면 system은 계속 실행하고 가능하면 affected hardware를 hot spare로 교체할 수 있습니다. Userspace process에서 난 오류라면 process를 kill하고 userspace가 restart하게 할 수도 있습니다.
Non-fatal error 처리는 보통 복잡하고 system administrator가 원하는 policy를 적용하기 위해 userspace application의 도움이 필요할 수 있습니다.
불량 component와 DIMM label 식별
95-159Hardware flaw 검출만으로는 충분하지 않습니다. 신뢰성을 회복하려면 교체해야 할 최소 교체 단위, 즉 Minimal Replaceable Unit(MRU)을 정확히 찾아야 합니다. 따라서 error logging뿐 아니라 error message를 MRU의 silkscreen 또는 component label로 변환하는 mechanism이 필요합니다.
Memory는 현대 CPU가 성능을 위해 여러 module의 memory를 interlace하므로 특히 복잡합니다. DMI BIOS의 memory module label 목록은 `dmidecode`로 얻을 수 있습니다. 다음 desktop 예제는 DDR4 SO-DIMM 정보를 보여 줍니다.
Memory Device
Total Width: 64 bits
Data Width: 64 bits
Size: 16384 MB
Form Factor: SODIMM
Set: None
Locator: ChannelA-DIMM0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 2133 MHz
Rank: 2
Configured Clock Speed: 2133 MHz이 예제의 module은 `Bank Locator`가 지정한 `BANK 0`에 있습니다. `Total Width`와 `Data Width`가 모두 64bit이므로 error detection/correction용 추가 bit가 없습니다.
모든 system이 같은 field로 memory bank를 표시하지는 않습니다. 다음 오래된 server 예제에서는 `Locator`가 실제 label을 제공합니다.
Memory Device
Array Handle: 0x1000
Error Information Handle: Not Provided
Total Width: 72 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: DIMM
Set: 1
Locator: DIMM_A1
Bank Locator: Not Specified
Type: DDR3
Type Detail: Synchronous Registered (Buffered)
Speed: 1600 MHz
Rank: 2
Configured Clock Speed: 1600 MHz이 DDR3 RDIMM은 `Locator`의 `DIMM_A1`에 있습니다. Data width는 64bit, total width는 72bit이므로 추가 8bit를 error detection과 correction에 사용합니다. 이런 memory를 Error-correcting code memory, 즉 ECC memory라고 합니다.
더 어려운 점은 board label이 서로 다른 system이 완전히 같은 BIOS를 쓰는 경우도 드물지 않아 BIOS가 제공한 label과 실제 label이 맞지 않을 수 있다는 것입니다.
ECC 동작과 EDAC의 유래
160-220ECC memory는 error correction용 추가 bit를 가집니다. 앞의 64bit data width와 72bit total width 예제에서 추가 8bit를 `syndrome`이라고 합니다.
CPU가 data-width word 쓰기를 요청하면 memory controller는 Hamming code나 SECDED+ 같은 error-correction code로 syndrome을 실시간 계산해 total-width code를 만들고 memory module에 기록합니다.
읽을 때는 같은 ECC code로 total-width code를 data-width word와 syndrome으로 되돌립니다. Error가 있어도 data-width word는 CPU로 전달됩니다. Memory controller는 syndrome으로 error 여부와 수정 성공 여부를 판단해 수정되면 CE, 수정하지 못하면 UE로 분류합니다.
CE/UE 정보는 memory controller의 특수 register에 저장되며 BIOS, 특수 CPU, Linux EDAC driver가 읽을 수 있습니다. x86-64 CPU에서는 Machine Check Architecture(MCA)로도 가져올 수 있습니다.
일부 controller의 Lock-Step mode는 두 memory module을 묶어 128bit read/write를 수행하므로 correction bit가 16개가 되어 복구력이 커집니다. 대신 오류가 나면 어느 module이 원인인지 알 수 없어 둘 모두를 지목해야 합니다.
Mirror mode는 같은 data를 두 module에 쓰고 읽을 때 양쪽이 같은지 확인합니다. 오류 시 원인 module을 구분할 수 없어 두 module을 모두 지목하며, Lock-Step도 함께 쓰면 네 module을 지목합니다.
MCA의 자세한 설명은 kernel tree의 `Documentation/arch/x86/x86_64/machinecheck.rst`를 참조합니다.
EDAC subsystem은 out-of-tree 시절 `bluesmoke`라는 이름으로 `http://bluesmoke.sourceforge.net`에서 유지됐습니다. 해당 site는 이제 거의 고문서 보관용입니다. Kernel 2.6.16에 처음 upstream될 때 이름을 `EDAC`으로 바꿨습니다.
EDAC 목적, 범위, PCI, version, load
221-312`edac` kernel module의 목표는 Linux에서 실행 중인 computer system 내부의 hardware error를 감지하고 보고하는 것입니다.
주요 수집 대상은 memory CE와 UE이며 `edac_mc` device가 이를 수집합니다. CE를 감지·수집·보고하는 일은 미래 UE의 징후일 수 있지만 반드시 그런 것은 아닙니다. CE만 발생한 동안에는 아직 data가 손상되지 않아 system은 계속 동작할 수 있습니다.
그러나 CE를 보이는 memory module을 예방 정비로 미리 교체하면 UE와 system panic 가능성을 낮출 수 있습니다.
Kernel 2.6.23에는 non-memory ECC detector 상태를 수집해 sysfs로 userspace에 제공하는 `edac_device` class가 추가됐습니다. Architecture에 따라 L1/L2/L3 cache, DMA engine, fabric switch, main data-path switch, interconnect 등 여러 hardware path에 ECC detector가 있으며 hardware가 보고할 수 있다면 `edac_device`로 노출할 수 있습니다.
EDAC는 data transfer 중 오류를 찾기 위해 PCI device의 PCI Bus Parity와 SERR Error도 scan합니다. 다만 parity 생성·보고에 관한 PCI specification을 따르지 않는 adapter가 있습니다. Parity를 만들지 않을 vendor는 status bit를 0에 고정해야 하지만 그렇지 않으면 bit가 floating해 false positive가 생길 수 있습니다.
EDAC PCI scanner는 device sysfs attribute가 설정된 경우 해당 device의 parity/error scan을 건너뜁니다. Attribute 이름은 다음과 같습니다.
broken_parity_status이 attribute는 PCI device의 `/sys/devices/pci<XXX>/0000:XX:YY.Z` directory에 있습니다.
EDAC는 core module `edac_core.ko`와 여러 Memory Controller(MC) driver module로 구성됩니다. System에는 core와 한 MC driver가 load되며 core와 MC 또는 `edac_device` driver는 각각 독립된 version을 갖습니다. 따라서 system version을 보고할 때 둘 모두를 알려야 합니다.
EDAC가 kernel에 static link됐다면 load할 필요가 없습니다. Module로 build했다면 필요한 hardware-specific module을 `modprobe`하면 dependency가 core module을 함께 load합니다.
$ modprobe amd76x_edac이 예제는 `amd76x_edac.ko` memory-controller module과 `edac_mc.ko` core module을 함께 load합니다.
Sysfs와 Memory Controller model
313-427EDAC의 control·reporting sysfs interface는 `/sys/devices/system/edac`에 있습니다. 현재 `mc`는 memory-controller system, `pci`는 PCI control/status system을 나타냅니다.
| Directory | 역할 |
|---|---|
| mc | Memory controller system |
| pci | PCI control and status system |
각 `mc` device는 memory module 집합을 제어합니다. Module은 Chip-Select Row `csrowX`와 channel `chX` 표에 배치되며 csrow와 channel이 여러 개일 수 있습니다.
DIMM은 널리 쓰이는 memory-module 이름이지만 SO-DIMM, SIMM 같은 다른 package도 있습니다. UEFI 2.7의 CPER는 memory module을 SMBIOS Memory Device(Type 17)로 정의합니다. 이 문서와 EDAC는 package와 관계없이 모든 memory module을 `dimm`이라고 부릅니다.
Memory controller의 csrow 수는 motherboard layout, controller, module 특성에 따라 달라지며 8개가 흔합니다. Dual channel은 64bit system에서 CPU와 memory 사이에 128bit 전송을 가능하게 하고 FB-DIMM controller처럼 두 개보다 많은 channel을 지원할 수도 있습니다.
두 channel의 물리 DIMM pair가 rank별 csrow를 공유하는 예입니다.
A label은 channel 0, B label은 channel 1을 나타냅니다.
Slot label은 보통 motherboard에 silkscreen됩니다. 이 예제에서 A는 channel 0, B는 channel 1이며 물리 DIMM 하나에 csrow 두 개가 가능합니다. DIMM을 어느 slot에 꽂는지에 따라 csrow가 할당되고 channel마다 DIMM 하나를 꽂으면 csrow가 두 DIMM을 가로지릅니다.
DIMM은 single-rank 또는 dual-rank입니다. Rank는 채워진 csrow입니다. 두 dual-rank DIMM을 A0/B0에 꽂으면 csrow0과 csrow1이 모두 채워지고, single-rank 두 개면 csrow0만 채워집니다. 같은 pattern이 csrow2/3에도 반복됩니다. Module을 직접 식별하지 못하는 controller는 아래의 `rankX` directory를 사용합니다.
`/sys/devices/system/edac/mc` 아래에서 각 controller는 index X의 `mcX` directory로 표현됩니다.
EDAC mc root 아래에 controller instance가 나란히 생성됩니다.
각 `mcX` 아래에는 채워진 `csrowX`가 나타납니다.
csrow1이 없고 csrow2·3이 모두 있으면 앞 pair는 single-rank, 뒤 pair는 dual-rank임을 뜻합니다.
Dual-channel mode가 동작하려면 이 rank 배치가 두 channel 모두에 적용돼야 합니다. 각 `mcX`와 `csrowX` directory에는 EDAC control·attribute file이 있습니다.
mcX와 dimmX/rankX attribute
428-579`mcX` directory에는 해당 memory-controller instance의 EDAC control과 attribute가 있습니다. Sysfs API의 정식 설명은 `Documentation/ABI/testing/sysfs-devices-edac`을 참조합니다.
EDAC subsystem을 사용할 때는 `dimmX` 또는 `rankX` directory가 제공하는 정보를 보는 방식을 권장합니다. 일반적인 `/sys/devices/system/edac/` 구조는 다음처럼 controller와 per-DIMM attribute를 계층화합니다.
Controller counter와 DIMM별 식별·오류 attribute가 같은 mc instance 아래에 있습니다.
`dimmX/size`는 이 module이 관리하는 memory를 MB 단위로 표시합니다. `dimm_ue_count`는 해당 DIMM의 총 UE 수이며 `panic_on_ue`가 켜져 있으면 panic 때문에 counter가 증가할 기회가 없을 수 있습니다.
`dimm_ce_count`는 총 CE 수입니다. CE는 DIMM 고장의 초기 신호일 수 있으므로 0이 아닌 값을 monitoring하고 system administrator에게 보고하는 것이 중요합니다.
`dimm_dev_type`은 DIMM의 DRAM device 폭을 `x1`, `x2`, `x4`, `x8` 등으로 표시합니다. `dimm_edac_mode`는 사용 중인 error detection/correction 방식을 표시합니다.
`dimm_label`은 module에 물리 label을 지정하는 control file입니다. Error log에 실제 DIMM label을 넣어 UE panic 원인을 격리하는 데 필수적입니다. Boot 뒤 motherboard의 silkscreen slot을 정확히 식별하는 정보를 userspace가 지정해야 하며 현재 이 정보는 motherboard-specific입니다.
`dimm_location`은 controller가 module 위치를 식별하는 방식을 최대 세 level로 설명합니다. Module을 직접 식별하지 못하는 `rankX`는 `csrow/channel`, FB-DIMM controller는 `branch/channel/slot`, Nehalem 이후 Intel driver는 `channel/slot`을 사용합니다.
`dimm_mem_type`은 현재 memory 종류를 표시하며 보통 buffered 또는 unbuffered입니다. 예로 `Registered-DDR`, `Unbuffered-DDR`가 있습니다.
일부 controller는 module 식별 logic이 없어 `rankX` directory를 만들고 `csrowX`와 비슷하게 동작합니다. Modern Intel controller는 module을 직접 식별해 `dimmX`를 사용합니다.
Sysfs가 자동 생성하는 `power` directory와 `subsystem` symlink도 있을 수 있지만 현재 EDAC 목적에는 쓰이지 않습니다.
Legacy csrowX와 system logging
580-744`CONFIG_EDAC_LEGACY_SYSFS`가 켜지면 `csrowX` directory가 생깁니다. 이 API는 Rambus, FB-DIMM, modern Intel memory controller에서 제대로 동작하지 않아 `dimmX` 방식으로 대체되고 있습니다.
`csrowX/ue_count`는 해당 csrow의 총 UE 수입니다. `panic_on_ue`가 켜져 있으면 panic 때문에 증가하지 못할 수 있습니다. `ce_count`는 총 CE 수이며 DIMM 고장 초기 신호로 monitoring하고 관리자에게 보고해야 합니다.
`size_mb`는 csrow가 관리하는 MB 단위 memory 크기입니다. `mem_type`은 `Registered-DDR` 또는 `Unbuffered-DDR` 같은 memory 종류, `edac_mode`는 error detection/correction 방식, `dev_type`은 `x1`, `x2`, `x4`, `x8` 같은 DRAM device type을 표시합니다.
`ch0_ce_count`와 `ch0_ue_count`는 channel 0 DIMM의 CE/UE 수를 표시하고 `ch0_dimm_label`은 해당 DIMM에 물리 label을 지정합니다. Label은 boot 뒤 userspace가 motherboard silkscreen에 맞게 설정해야 하며 UE panic 원인 격리에 중요합니다.
`ch1_ce_count`, `ch1_ue_count`, `ch1_dimm_label`은 channel 1에 같은 기능을 제공합니다. 원문은 `ch1_ue_count` 설명에서 channel 0이라고 적지만 attribute 문맥상 channel 1용 counter입니다.
UE와 CE logging이 켜져 있으면 system log에 다음과 같은 감지 정보가 기록됩니다.
EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, channel 1 "DIMM_B1": amd76x_edac
EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0, channel 1 "DIMM_B1": amd76x_edac한 log line이 controller, error 위치, granularity, syndrome, DIMM label과 driver message를 전달합니다.
정보가 없는 UE/CE message는 memory controller와 error type, `no info` 알림, optional driver-specific message만 포함합니다.
PCI parity와 EDAC module parameter
745-875Header Type 00 device에서는 parity enable 여부와 관계없이 primary status의 parity error를 확인합니다. Specification상 일부 경우에는 parity가 생성되기 때문입니다. Header Type 01 bridge에서는 secondary status register도 확인해 bridge 반대편 bus의 parity error를 찾습니다.
`/sys/devices/system/edac/pci/check_pci_parity`에 1을 쓰면 PCI Bus Parity scan을 켜고 0을 쓰면 끕니다.
echo "1" >/sys/devices/system/edac/pci/check_pci_parityecho "0" >/sys/devices/system/edac/pci/check_pci_parity`pci_parity_count`는 감지한 parity error 수를 표시합니다.
`edac_mc_panic_on_ue`는 UE 발생 시 machine을 panic시킵니다. 무엇이 수정되지 않았는지 알 수 없고 OS context가 망가져 계속 실행하면 더 큰 corruption이 생길 수 있어 일반적으로 바람직합니다. Kernel에 MCE가 구성되면 EDAC는 UE를 보지 못합니다.
module/kernel parameter: edac_mc_panic_on_ue=[0|1]echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue`edac_mc_log_ue`는 UE를 kernel system message log에 기록합니다. Logging을 꺼도 UE statistic은 누적됩니다.
module/kernel parameter: edac_mc_log_ue=[0|1]echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue`edac_mc_log_ce`는 CE를 kernel system message log에 기록합니다. Logging을 꺼도 CE statistic은 누적됩니다.
module/kernel parameter: edac_mc_log_ce=[0|1]echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce`edac_mc_poll_msec`는 error information polling period를 millisecond로 지정합니다. 너무 작으면 resource를 낭비하고 너무 크면 필요한 처리가 늦고 위치 식별 정보가 유실될 수 있습니다. 기본값은 1000ms, 즉 초당 한 번이며 bandwidth가 중요한 system은 늘릴 수 있습니다.
module/kernel parameter: edac_mc_poll_msec=[0|1]echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec`panic_on_pci_parity`는 parity error 감지 시 panic 여부를 제어합니다. Module parameter 이름은 `edac_panic_on_pci_pe`이며 runtime에 1 또는 0을 쓸 수 있습니다.
edac_panic_on_pci_pe=[0|1]echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_peecho "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_peEDAC device, instance, block
876-985`edac_pci.h`에는 `EDAC_DEVICE`용 `edac_device` structure와 API가 있습니다. Userspace는 sysfs로 접근하며 새 device는 `/sys/devices/system/edac` 아래에 나타납니다.
Out-of-tree `test_device_edac` 예제는 자신을 다음 path에 설치합니다.
/sys/devices/system/edac/test-instance그 directory에는 control, symlink, 하나 이상의 `instance` directory가 있습니다. 기본 control은 CE logging `log_ce`, UE logging `log_ue`, UE 시 panic하는 `panic_on_ue`(기본 off, startup script로 설정 가능), poll 주기 `poll_msec`입니다.
| Control | 의미 |
|---|---|
| log_ce | CE event logging boolean |
| log_ue | UE event logging boolean |
| panic_on_ue | UE에서 panic; 기본 off |
| poll_msec | Event poll cycle 간격 |
예제 device의 custom `test_bits` control은 현재 아무 동작도 하지 않고 설치 방법만 보여 줍니다. Port한 driver는 hardware-specific control이나 attribute를 추가할 수 있습니다. 한 out-of-tree driver는 hardware injection register를 위한 ERROR INJECTION control을 여기에 둡니다. Symlink는 이 edac_device에 등록된 `struct dev`를 가리킵니다.
Device root 아래에 하나 이상의 instance가 있고 각 instance는 하위 block counter를 합산합니다.
각 instance에는 더 깊은 subdirectory counter의 합계인 `ce_count`와 `ue_count`가 있습니다.
Instance마다 0개 이상의 block이 있으며 block별 CE/UE counter를 가집니다.
Block의 `ce_count`와 `ue_count`는 monitoring 대상 hardware block에서 발생한 CE와 UE 수를 셉니다.
`test_device_edac`는 네 attribute와 한 control을 더합니다. `test-block-bits-0`은 poll마다 증가하고, `-1`은 10 cycle마다 증가하며 `-0`을 0으로 만듭니다. `-2`는 100 cycle마다 증가하며 `-1`을 reset하고, `-3`은 1000 cycle마다 증가하며 `-2`를 reset합니다.
`reset-counters`에 어떤 값이든 쓰면 위 counter를 모두 reset합니다. 이 sample은 다른 developer가 자신의 hardware system용 독자 driver를 만드는 기준이 되며 source는 `http://bluesmoke.sourceforge.net`의 EDAC project site에 있습니다.
Nehalem 이후 Intel MC mapping
986-1036오래된 Intel architecture에서는 memory controller가 North Bridge chipset 일부였습니다. Nehalem, Sandy Bridge, Ivy Bridge, Haswell, Skylake 이후에는 향상된 MC가 CPU 안에 통합됐습니다. 이 절은 `i7core_edac`, `sb_edac`, `sbx_edac` 같은 driver의 차이를 설명합니다.
Xeon E7 family는 Intel Scalable Memory Buffer라는 별도 memory-controller chip을 사용하므로 이 절이 적용되지 않습니다.
QuickPath Interconnect(QPI)마다 MC 하나가 있습니다. Driver에서 `socket`은 QPI 하나를 뜻하며 physical CPU socket과 연결됩니다. 각 MC는 physical read channel 3개, write channel 3개, logical channel 3개를 가지지만 driver는 현재 channel 3개로 봅니다. Channel마다 DIMM을 최대 3개 가질 수 있습니다.
Hardware가 알려 주는 최소 단위는 DIMM이고 csrow 정보는 없습니다. EDAC API의 최소 단위가 csrow이므로 driver는 channel/DIMM 조합을 서로 다른 csrow에 순서대로 mapping합니다. 예제 hardware layout은 다음과 같습니다.
Ch0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs
dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400
Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs
dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs
dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400Driver는 이를 다음처럼 mapping합니다.
csrow0: channel 0, dimm0
csrow1: channel 0, dimm1
csrow2: channel 1, dimm0
csrow3: channel 2, dimm0따라서 csrow마다 DIMM 하나를 export하고 각 QPI를 별도 memory controller로 export합니다.
Intel memory error injection
1037-1111새 MC는 driver test를 위한 error injection 기능을 갖고 driver는 `/sys/devices/system/edac/mc/mc?/` 아래 node로 이를 제공합니다.
`inject_addrmatch/*`는 error-injection mask register를 제어합니다. Match할 address 특성은 다음과 같습니다.
dimm = the affected dimm. Numbers are relative to a channel;
rank = the memory rank;
channel = the channel that will generate an error;
bank = the affected bank;
page = the page address;
column (or col) = the address column.각 값은 `any`로 설정해 모든 valid value와 match할 수 있고 driver init 때 모두 `any`입니다. Channel·bank·page·column은 무엇이든 허용하면서 DIMM 2의 rank 1에 error를 만들려면 다음처럼 지정합니다.
echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank기본 `any` 동작으로 되돌리는 명령은 다음과 같습니다.
echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank`inject_eccmask`는 문제가 생길 bit를 정합니다. `inject_section`은 error를 넣을 ECC cache section을 지정합니다.
3 for both
2 for the highest
1 for the lowest`inject_type`은 error type bit 조합을 지정합니다.
bit 0 - repeat
bit 1 - ecc
bit 2 - parity`inject_enable`에 0이 아닌 값을 쓰면 error 생성을 시작합니다. 모든 injection variable은 읽을 수 있고 쓰기에는 root 권한이 필요합니다.
Datasheet는 `inject_addrmatch`와 일치하는 address에 write한 뒤에만 error가 생긴다고 하지만 실제로는 read도 error를 만드는 것으로 보입니다. Socket 0, channel 2의 모든 DIMM/address write에 error를 만드는 예는 다음과 같습니다.
echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel
echo 2 >/sys/devices/system/edac/mc/mc0/inject_type
echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask
echo 3 >/sys/devices/system/edac/mc/mc0/inject_section
echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable
dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/nullSocket 1에서는 위 명령의 `mc0`을 `mc1`로 바꿉니다. 생성된 error message 예는 다음과 같습니다.
EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error))Intel corrected-error counter
1112-1157새 MC에는 memory error를 세는 register가 있습니다. Driver는 Registered DIMM에서 이 register를 사용해 Corrected Error를 보고합니다.
기본 counter는 Unregistered DIMM에서 동작하지 않습니다. Chipset에는 granularity가 더 낮지만 UDIMM에서도 동작하는 counter가 있어 driver가 `all_channel_counts/`로 노출합니다.
$ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0
0
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1
0
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2
0서로 다른 csrow라도 DIMM number가 같으면 같은 counter가 증가합니다. Mapping은 다음과 같습니다.
csrow0: channel 0, dimm0
csrow1: channel 0, dimm1
csrow2: channel 1, dimm0
csrow3: channel 2, dimm0첫 번째 DIMM의 error가 csrow0, csrow2, csrow3 어디에서 발생해도 `udimm0`이 증가합니다. 같은 방식으로 두 번째 DIMM은 `udimm1`, 세 번째 DIMM은 `udimm2`를 증가시킵니다.
Standard error counter는 driver가 mcelog error를 받을 때 생성됩니다. UDIMM은 software로 세므로 일부 error가 유실될 수 있고 RDIMM에서는 hardware register 내용을 표시합니다.
amd64_edac 참고 문서
1158-1204`amd64_edac` module은 `http://support.amd.com/en-us/search/tech-docs`에서 제공되던 다음 AMD 문서를 바탕으로 합니다.
| 번호 | 문서 | Publication | Revision / Date | Link |
|---|---|---|---|---|
| 1 | BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processors | 26094 | 3.26 | http://support.amd.com/TechDocs/26094.PDF |
| 2 | BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors | 32559 | 3.00 / May 2006 | http://support.amd.com/TechDocs/32559.pdf |
| 3 | BKDG For AMD Family 10h Processors | 31116 | 3.00 / September 07, 2007 | http://support.amd.com/TechDocs/31116.pdf |
| 4 | BKDG for AMD Family 15h Models 30h-3Fh | 49125 | 3.06 / 2/12/2015 | http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf |
| 5 | BKDG for AMD Family 15h Models 60h-6Fh | 50742 | 3.01 / 7/23/2015 | http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf |
| 6 | BKDG for AMD Family 16h Models 00h-0Fh | 48751 | 3.03 / 2/23/2015 | http://support.amd.com/TechDocs/48751_16h_bkdg.pdf |
기여자와 변경 이력
1205-1223Doug Thompson `<dougthompson@xmission.com>`이 2005년 12월 7일 이 문서를 작성하고 2007년 7월 17일 갱신했습니다.
Mauro Carvalho Chehab은 2009년 8월 5일 Nehalem interface를 추가했고 2016년 10월 26일 ReST 변환과 Nehalem section 정리를 수행했습니다.
EDAC author와 maintainer는 Doug Thompson, Dave Jiang, Dave Peterson 등과 Mauro Carvalho Chehab, Borislav Petkov이며 original author는 Thayne Harbaugh입니다.
요약과 해설
main.rst:1-1223Linux RAS는 hardware fault를 검출·수정하고 degradation 추세를 userspace에 노출해 CE 단계에서 예방 정비를 가능하게 합니다. UE는 context corruption 위험 때문에 panic policy와 결합되는 경우가 많습니다.
운영 관점의 핵심은 EDAC counter 자체보다 error를 교체 가능한 물리 DIMM label로 연결하는 것입니다. Modern driver는 `dimmX`를 권장하며 `csrowX` legacy API는 일부 memory architecture에서 정확하지 않아 deprecated되고 있습니다.