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Linux 6.18.37 · ABI / testing

CoreSight ETM3x and PTM trace source sysfs ABI

ETM3x·PTM trace source enable, address comparators, counters, context IDs, trace events·mode·capabilities, sequencer, stream identity와 management register views를 설명합니다.

Source pathDocumentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
Source versionLinux v6.18.37
TranslationDUJINLABS 전문 번역 + 해설

요약·해설과 원문, 전문 번역을 서로 분리했습니다. API 이름, symbol, source path는 원문 표기를 사용합니다.

1. 요약·해설

원문의 핵심 논리와 kernel programming 관점의 보충 설명입니다. 아래의 전문 번역과는 별도로 작성했습니다.

Trace source와 address comparator programming

sysfs-bus-coresight-devices-etm3x:1-59

enable_source는 configured ETM/PTM을 identified sink에 연결하고, addr_idx와 access type·range·single·start·stop attributes가 selected address comparator를 program합니다.

Counter와 context ID selectors

sysfs-bus-coresight-devices-etm3x:61-113

cntr_idx는 event·value·reload value·reload event register를, ctxid_idx는 context comparator PID를 선택하며 mask는 모든 context ID comparators에 적용됩니다.

Trace events, mode, capabilities와 reset

sysfs-bus-coresight-devices-etm3x:115-171

Enable event, ETM status, FIFO threshold와 driver-specific mode를 제어하고 ETMCCR fields에서 comparator·counter 수를 읽으며 reset은 boot configuration으로 되돌립니다.

Three-state trace sequencer

sysfs-bus-coresight-devices-etm3x:173-219

seq_12·13·21·23·31·32_event가 states 1·2·3 사이의 모든 directed transitions를 정의하고 curr_seq_state가 current state를 제공합니다.

Synchronization, timestamps, trace identity와 CPU

sysfs-bus-coresight-devices-etm3x:221-258

sync frequency, timestamp insertion event, stream trace ID, trigger event, tracer CPU affinity와 hardware context label을 제공합니다.

ETM management register views

sysfs-bus-coresight-devices-etm3x:260-328

mgmt files는 ETM configuration, system configuration, ID, control, trace ID, enable event, start/stop과 enable-control registers를 exact hardware offsets에서 직접 읽습니다.

2. 영어 원문 전체

번역 기준이 된 Linux v6.18.37 원문입니다. 줄 번호는 이 버전의 파일 좌표입니다.

원문 전체 펼치기
1 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source
2 Date: November 2014
3 KernelVersion: 3.19
4 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
5 Description: (RW) Enable/disable tracing on this specific trace entiry.
6 Enabling a source implies the source has been configured
7 properly and a sink has been identidifed for it. The path
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
10
11 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx
12 Date: November 2014
13 KernelVersion: 3.19
14 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
15 Description: Select which address comparator or pair (of comparators) to
16 work with.
17
18 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype
19 Date: November 2014
20 KernelVersion: 3.19
21 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
22 Description: (RW) Used in conjunction with @addr_idx. Specifies
23 characteristics about the address comparator being configure,
24 for example the access type, the kind of instruction to trace,
25 processor context ID to trigger on, etc. Individual fields in
26 the access type register may vary on the version of the trace
27 entity.
28
29 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range
30 Date: November 2014
31 KernelVersion: 3.19
32 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
33 Description: (RW) Used in conjunction with @addr_idx. Specifies the range of
34 addresses to trigger on. Inclusion or exclusion is specified
35 in the corresponding access type register.
36
37 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single
38 Date: November 2014
39 KernelVersion: 3.19
40 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
41 Description: (RW) Used in conjunction with @addr_idx. Specifies the single
42 address to trigger on, highly influenced by the configuration
43 options of the corresponding access type register.
44
45 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start
46 Date: November 2014
47 KernelVersion: 3.19
48 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
49 Description: (RW) Used in conjunction with @addr_idx. Specifies the single
50 address to start tracing on, highly influenced by the
51 configuration options of the corresponding access type register.
52
53 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop
54 Date: November 2014
55 KernelVersion: 3.19
56 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
57 Description: (RW) Used in conjunction with @addr_idx. Specifies the single
58 address to stop tracing on, highly influenced by the
59 configuration options of the corresponding access type register.
60
61 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx
62 Date: November 2014
63 KernelVersion: 3.19
64 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
65 Description: (RW) Specifies the counter to work on.
66
67 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event
68 Date: November 2014
69 KernelVersion: 3.19
70 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
71 Description: (RW) Used in conjunction with cntr_idx, give access to the
72 counter event register.
73
74 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val
75 Date: November 2014
76 KernelVersion: 3.19
77 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
78 Description: (RW) Used in conjunction with cntr_idx, give access to the
79 counter value register.
80
81 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_val
82 Date: November 2014
83 KernelVersion: 3.19
84 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
85 Description: (RW) Used in conjunction with cntr_idx, give access to the
86 counter reload value register.
87
88 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_event
89 Date: November 2014
90 KernelVersion: 3.19
91 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
92 Description: (RW) Used in conjunction with cntr_idx, give access to the
93 counter reload event register.
94
95 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_idx
96 Date: November 2014
97 KernelVersion: 3.19
98 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
99 Description: (RW) Specifies the index of the context ID register to be
100 selected.
101
102 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_mask
103 Date: November 2014
104 KernelVersion: 3.19
105 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
106 Description: (RW) Mask to apply to all the context ID comparator.
107
108 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_pid
109 Date: November 2014
110 KernelVersion: 3.19
111 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
112 Description: (RW) Used with the ctxid_idx, specify with context ID to trigger
113 on.
114
115 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_event
116 Date: November 2014
117 KernelVersion: 3.19
118 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
119 Description: (RW) Defines which event triggers a trace.
120
121 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/etmsr
122 Date: November 2014
123 KernelVersion: 3.19
124 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
125 Description: (RW) Gives access to the ETM status register, which holds
126 programming information and status on certains events.
127
128 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/fifofull_level
129 Date: November 2014
130 KernelVersion: 3.19
131 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
132 Description: (RW) Number of byte left in the fifo before considering it full.
133 Depending on the tracer's version, can also hold threshold for
134 data suppression.
135
136 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mode
137 Date: November 2014
138 KernelVersion: 3.19
139 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
140 Description: (RW) Interface with the driver's 'mode' field, controlling
141 various aspect of the trace entity such as time stamping,
142 context ID size and cycle accurate tracing. Driver specific
143 and bound to change depending on the driver.
144
145 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_addr_cmp
146 Date: November 2014
147 KernelVersion: 3.19
148 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
149 Description: (Read) Provides the number of address comparators pairs accessible
150 on a trace unit, as specified by bit 3:0 of register ETMCCR.
151
152 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_cntr
153 Date: November 2014
154 KernelVersion: 3.19
155 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
156 Description: (Read) Provides the number of counters accessible on a trace unit,
157 as specified by bit 15:13 of register ETMCCR.
158
159 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_ctxid_cmp
160 Date: November 2014
161 KernelVersion: 3.19
162 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
163 Description: (Read) Provides the number of context ID comparator available on a
164 trace unit, as specified by bit 25:24 of register ETMCCR.
165
166 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/reset
167 Date: November 2014
168 KernelVersion: 3.19
169 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
170 Description: (Write) Cancels all configuration on a trace unit and set it back
171 to its boot configuration.
172
173 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_12_event
174 Date: November 2014
175 KernelVersion: 3.19
176 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
177 Description: (RW) Defines the event that causes the sequencer to transition
178 from state 1 to state 2.
179
180 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_13_event
181 Date: November 2014
182 KernelVersion: 3.19
183 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
184 Description: (RW) Defines the event that causes the sequencer to transition
185 from state 1 to state 3.
186
187 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_21_event
188 Date: November 2014
189 KernelVersion: 3.19
190 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
191 Description: (RW) Defines the event that causes the sequencer to transition
192 from state 2 to state 1.
193
194 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_23_event
195 Date: November 2014
196 KernelVersion: 3.19
197 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
198 Description: (RW) Defines the event that causes the sequencer to transition
199 from state 2 to state 3.
200
201 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_31_event
202 Date: November 2014
203 KernelVersion: 3.19
204 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
205 Description: (RW) Defines the event that causes the sequencer to transition
206 from state 3 to state 1.
207
208 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_32_event
209 Date: November 2014
210 KernelVersion: 3.19
211 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
212 Description: (RW) Defines the event that causes the sequencer to transition
213 from state 3 to state 2.
214
215 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/curr_seq_state
216 Date: November 2014
217 KernelVersion: 3.19
218 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
219 Description: (Read) Holds the current state of the sequencer.
220
221 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/sync_freq
222 Date: November 2014
223 KernelVersion: 3.19
224 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
225 Description: (RW) Holds the trace synchronization frequency value - must be
226 programmed with the various implementation behavior in mind.
227
228 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/timestamp_event
229 Date: November 2014
230 KernelVersion: 3.19
231 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
232 Description: (RW) Defines an event that requests the insertion of a timestamp
233 into the trace stream.
234
235 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/traceid
236 Date: November 2014
237 KernelVersion: 3.19
238 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
239 Description: (RO) Holds the trace ID that will appear in the trace stream
240 coming from this trace entity.
241
242 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/trigger_event
243 Date: November 2014
244 KernelVersion: 3.19
245 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
246 Description: (RW) Define the event that controls the trigger.
247
248 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cpu
249 Date: October 2015
250 KernelVersion: 4.4
251 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
252 Description: (RO) Holds the cpu number this tracer is affined to.
253
254 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/label
255 Date: Aug 2025
256 KernelVersion 6.18
257 Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
258 Description: (Read) Show hardware context information of device.
259
260 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr
261 Date: September 2015
262 KernelVersion: 4.4
263 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
264 Description: (RO) Print the content of the ETM Configuration Code register
265 (0x004). The value is read directly from the HW.
266
267 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccer
268 Date: September 2015
269 KernelVersion: 4.4
270 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
271 Description: (RO) Print the content of the ETM Configuration Code Extension
272 register (0x1e8). The value is read directly from the HW.
273
274 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmscr
275 Date: September 2015
276 KernelVersion: 4.4
277 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
278 Description: (RO) Print the content of the ETM System Configuration
279 register (0x014). The value is read directly from the HW.
280
281 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmidr
282 Date: September 2015
283 KernelVersion: 4.4
284 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
285 Description: (RO) Print the content of the ETM ID register (0x1e4). The
286 value is read directly from the HW.
287
288 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmcr
289 Date: September 2015
290 KernelVersion: 4.4
291 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
292 Description: (RO) Print the content of the ETM Main Control register (0x000).
293 The value is read directly from the HW.
294
295 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtraceidr
296 Date: September 2015
297 KernelVersion: 4.4
298 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
299 Description: (RO) Print the content of the ETM Trace ID register (0x200).
300 The value is read directly from the HW.
301
302 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmteevr
303 Date: September 2015
304 KernelVersion: 4.4
305 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
306 Description: (RO) Print the content of the ETM Trace Enable Event register
307 (0x020). The value is read directly from the HW.
308
309 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtsscr
310 Date: September 2015
311 KernelVersion: 4.4
312 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
313 Description: (RO) Print the content of the ETM Trace Start/Stop Control
314 register (0x018). The value is read directly from the HW.
315
316 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr1
317 Date: September 2015
318 KernelVersion: 4.4
319 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
320 Description: (RO) Print the content of the ETM Enable Control #1
321 register (0x024). The value is read directly from the HW.
322
323 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr2
324 Date: September 2015
325 KernelVersion: 4.4
326 Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
327 Description: (RO) Print the content of the ETM Enable Control #2
328 register (0x01c). The value is read directly from the HW.
329

3. 한국어 전문 번역

영어 원문의 문단 순서와 의미를 유지한 전체 번역입니다. 코드, 함수명, symbol과 URL은 원문 표기를 유지합니다.

ETM/PTM source enable과 address comparators

1-59
공통 항목내용
Date2014년 11월
KernelVersion3.19
ContactMathieu Poirier <mathieu.poirier@linaro.org>
적용 범위별도 metadata가 있는 cpu·label·mgmt를 제외한 lines 1-247 attributes
What suffixAccess전문 번역
enable_sourceRW이 특정 trace entity의 tracing을 enable 또는 disable합니다. Source를 enable한다는 것은 source가 올바르게 configure되었고 sink가 identified되었음을 전제로 합니다. Source와 sink를 연결하는 CoreSight component path는 CoreSight framework가 자동으로 configure하고 manage합니다.
addr_idxSelector작업할 address comparator 또는 comparator pair를 선택합니다.
addr_acctypeRWaddr_idx와 함께 사용합니다. Configure할 address comparator의 access type, trace할 instruction 종류, trigger할 processor context ID 같은 characteristics를 지정합니다. Access type register의 개별 field는 trace entity version에 따라 다를 수 있습니다.
addr_rangeRWaddr_idx와 함께 사용합니다. Trigger할 address range를 지정합니다. Inclusion 또는 exclusion은 corresponding access type register에서 지정합니다.
addr_singleRWaddr_idx와 함께 사용합니다. Trigger할 single address를 지정하며 corresponding access type register의 configuration options에 큰 영향을 받습니다.
addr_startRWaddr_idx와 함께 사용합니다. Tracing을 시작할 single address를 지정하며 corresponding access type register의 configuration options에 큰 영향을 받습니다.
addr_stopRWaddr_idx와 함께 사용합니다. Tracing을 중지할 single address를 지정하며 corresponding access type register의 configuration options에 큰 영향을 받습니다.

위 suffix는 모두 /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ 아래의 file입니다.

ETM/PTM source와 address selector
Configured ETM or PTM sourceIdentified sinkEnable sourceFramework-managed CoreSight pathTrace stream
Write addr_idxSelect comparator or pairSet addr_acctypeProgram range, single, start or stop address

Sink를 먼저 identify한 뒤 framework가 path를 구성하며 addr_idx가 comparator-specific programming files의 target을 정한다.

Counter registers와 context ID comparators

61-113
What suffixAccess전문 번역
cntr_idxRW작업할 counter를 지정합니다.
cntr_eventRWcntr_idx와 함께 사용하며 counter event register에 access합니다.
cntr_valRWcntr_idx와 함께 사용하며 counter value register에 access합니다.
cntr_rld_valRWcntr_idx와 함께 사용하며 counter reload value register에 access합니다.
cntr_rld_eventRWcntr_idx와 함께 사용하며 counter reload event register에 access합니다.
ctxid_idxRW선택할 context ID register의 index를 지정합니다.
ctxid_maskRW모든 context ID comparator에 적용할 mask입니다.
ctxid_pidRWctxid_idx와 함께 사용하며 trigger할 context ID를 지정합니다.
Indexed counter and context-ID programming
cntr_idxSelected counterevent, value, reload value and reload event
ctxid_idxSelected context ID comparatorctxid_pid trigger value
ctxid_maskMask applied to all context ID comparators

Counter와 context comparator는 selector file로 target을 고른 뒤 관련 register view를 read/write한다.

Trace control, resource counts와 reset

115-171
What suffixAccess전문 번역
enable_eventRW어떤 event가 trace를 trigger하는지 정의합니다.
etmsrRWProgramming information과 특정 events의 status를 담는 ETM status register에 access합니다.
fifofull_levelRWFIFO를 full로 간주하기 전 남아 있는 byte 수입니다. Tracer version에 따라 data suppression threshold도 담을 수 있습니다.
modeRWDriver의 mode field와 interface하며 timestamping, context ID size, cycle-accurate tracing 같은 trace entity의 여러 측면을 제어합니다. Driver-specific이고 driver에 따라 바뀔 수 있습니다.
nr_addr_cmpReadETMCCR register bits [3:0]이 지정하는 trace unit에서 access 가능한 address comparator pairs 수를 제공합니다.
nr_cntrReadETMCCR register bits [15:13]이 지정하는 trace unit에서 access 가능한 counters 수를 제공합니다.
nr_ctxid_cmpReadETMCCR register bits [25:24]가 지정하는 trace unit의 available context ID comparators 수를 제공합니다.
resetWriteTrace unit의 모든 configuration을 cancel하고 boot configuration으로 되돌립니다.

ETM three-state sequencer events

173-219
What suffixAccess전문 번역
seq_12_eventRWSequencer를 state 1에서 state 2로 transition시키는 event를 정의합니다.
seq_13_eventRWSequencer를 state 1에서 state 3으로 transition시키는 event를 정의합니다.
seq_21_eventRWSequencer를 state 2에서 state 1로 transition시키는 event를 정의합니다.
seq_23_eventRWSequencer를 state 2에서 state 3으로 transition시키는 event를 정의합니다.
seq_31_eventRWSequencer를 state 3에서 state 1로 transition시키는 event를 정의합니다.
seq_32_eventRWSequencer를 state 3에서 state 2로 transition시키는 event를 정의합니다.
curr_seq_stateReadSequencer의 current state를 담습니다.
ETM sequencer state transitions
State 1seq_12_eventState 2
State 1seq_13_eventState 3
State 2seq_21_eventState 1
State 2seq_23_eventState 3
State 3seq_31_eventState 1
State 3seq_32_eventState 2
Sequencercurr_seq_stateCurrent state

States 1, 2, 3 사이의 모든 directed transition이 각 seq_XY_event attribute로 독립 정의된다.

Synchronization, timestamp, trigger와 trace identity

221-258
What suffixAccess전문 번역
sync_freqRWTrace synchronization frequency value를 담습니다. 여러 implementation behavior를 고려하여 program해야 합니다.
timestamp_eventRWTrace stream에 timestamp 삽입을 요청하는 event를 정의합니다.
traceidRO이 trace entity에서 나오는 trace stream에 나타날 trace ID를 담습니다.
trigger_eventRWTrigger를 제어하는 event를 정의합니다.
WhatDateKernelVersionContact전문 번역
/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cpu2015년 10월4.4Mathieu Poirier <mathieu.poirier@linaro.org>(RO) 이 tracer가 affined된 CPU number를 담습니다.
/sys/bus/coresight/devices/<memory_map>.[etm|ptm]/label2025년 8월6.18Mao Jinlong <quic_jinlmao@quicinc.com>(Read) Device의 hardware context information을 보여 줍니다.

ETM hardware management registers

260-328
공통 항목내용
Date2015년 9월
KernelVersion4.4
ContactMathieu Poirier <mathieu.poirier@linaro.org>
What suffixRegisterOffset전문 번역
mgmt/etmccrETM Configuration Code0x004(RO) Hardware에서 직접 읽은 register content를 출력합니다.
mgmt/etmccerETM Configuration Code Extension0x1e8(RO) Hardware에서 직접 읽은 register content를 출력합니다.
mgmt/etmscrETM System Configuration0x014(RO) Hardware에서 직접 읽은 register content를 출력합니다.
mgmt/etmidrETM ID0x1e4(RO) Hardware에서 직접 읽은 register content를 출력합니다.
mgmt/etmcrETM Main Control0x000(RO) Hardware에서 직접 읽은 register content를 출력합니다.
mgmt/etmtraceidrETM Trace ID0x200(RO) Hardware에서 직접 읽은 register content를 출력합니다.
mgmt/etmteevrETM Trace Enable Event0x020(RO) Hardware에서 직접 읽은 register content를 출력합니다.
mgmt/etmtsscrETM Trace Start/Stop Control0x018(RO) Hardware에서 직접 읽은 register content를 출력합니다.
mgmt/etmtecr1ETM Enable Control #10x024(RO) Hardware에서 직접 읽은 register content를 출력합니다.
mgmt/etmtecr2ETM Enable Control #20x01c(RO) Hardware에서 직접 읽은 register content를 출력합니다.

모든 management path는 /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ 아래에 있습니다.